Three-dimensional integrated circuit

Three-dimensional integrated circuit

In electronics, a three-dimensional integrated circuit (3D IC, 3D-IC, or 3-D IC) is a chip in which two or more layers of active electronic components are integrated both vertically and horizontally into a single circuit. The semiconductor industry is pursuing this promising technology in many different forms, but it is not yet widely used; consequently, the definition is still somewhat fluid.

Contents

3D ICs vs. 3D packaging

3D packaging saves space by stacking separate chips in a single package. This packaging, known as System in Package (SiP) or Chip Stack MCM, does not integrate the chips into a single circuit. The chips in the package communicate using off-chip signaling, much as if they were mounted in separate packages on a normal circuit board. In contrast, a 3D IC is a single chip. All components on the layers communicate using on-chip signaling, whether vertically or horizontally. A 3D IC bears the same relation to a 3D package that a SoC bears to a circuit board.

Notable 3D chips

The Teraflops Research Chip introduced in 2007 by Intel is an experimental 80-core design with stacked memory. Due to the high demand for memory bandwidth, a traditional IO approach would consume 10 to 25W.[1] To improve upon that, Intel designers implemented a TSV-based memory bus. Each core is connected to one memory tile in the SRAM die with a link that provides 12 GB/s bandwidth, resulting in a total bandwidth of 1 TB/s while consuming only 2.2W.

In 2004, Intel presented a 3D version of the Pentium 4 CPU.[2] The chip was manufactured with two dies using face-to-face stacking, which allowed a dense via structure. Backside TSVs are used for IO and power supply. For the 3D floorplan, designers manually arranged functional blocks in each die aiming for power reduction and performance improvement. Splitting large and high-power blocks and careful rearrangement allowed to limit thermal hotspots. The 3D design provides 15% performance improvement (due to eliminated pipeline stages) and 15% power saving (due to eliminated repeaters and reduced wiring) compared to the 2D Pentium 4.

An academic implementation of a 3D processor was presented in 2008 at the University of Rochester by Professor Eby Friedman and his students. The chip runs at a 1.4 GHz and it was designed for optimized vertical processing between the stacked chips which gives the 3D processor abilities that the traditional one layered chip could not reach.[3] One challenge in manufacturing of the three-dimensional chip was to make all of the layers work in harmony without any obstacles that would interfere with a piece of information traveling from one layer to another.[4]

Manufacturing technologies

As of 2008 there are four ways to build a 3D IC:

Monolithic – Electronic components and their connections (wiring) are built in layers on a single semiconductor wafer, which is then diced into 3D ICs. There is only one substrate, hence no need for aligning, thinning, bonding, or through-silicon vias. Applications of this method are currently limited because creating normal transistors requires enough heat to destroy any existing wiring. This monolithic 3D-IC technology has been researched at Stanford university under a DARPA sponsored grant.

Wafer-on-Wafer – Electronic components are built on two or more semiconductor wafers, which are then aligned, bonded, and diced into 3D ICs. Each wafer may be thinned before or after bonding. Vertical connections are either built into the wafers before bonding or else created in the stack after bonding. These “through-silicon vias” (TSVs) pass through the silicon substrate(s) between active layers and/or between an active layer and an external bond pad. Wafer-on-wafer bonding can reduce yields, since if any 1 of N chips in a 3D IC are defective, the entire 3D IC will be defective. Moreover, the wafers must be the same size – but many exotic materials (e.g. III-Vs) are manufactured on much smaller wafers than CMOS logic or DRAM (typically 300mm), complicating heterogeneous integration.

Die-on-Wafer – Electronic components are built on two semiconductor wafers. One wafer is diced; the singulated dice are aligned and bonded onto die sites of the second wafer. As in the wafer-on-wafer method, thinning and TSV creation are performed either before or after bonding. Additional dice may be added to the stacks before dicing.

Die-on-Die – Electronic components are built on multiple dice, which are then aligned and bonded. Thinning and TSV creation may be done before or after bonding. One advantage of die-on-die is that each component die can be tested first, so that one bad die does not ruin an entire stack [5]. Moreover, each die in the 3D IC can be binned beforehand, so that they can be mixed and matched to optimize power consumption and performance (e.g. matching multiple dice from the low power process corner for a mobile application).

Benefits

Traditional scaling of semiconductor chips also improves signal propagation speed. However, scaling from current manufacturing and chip-design technologies has become more difficult, in part because of power-density constraints, and in part because interconnects do not become faster while transistors do [6] 3-D integrated circuits were proposed invented to address the scaling challenge by stacking 2-D dies and connecting them in the 3rd dimension. This promises to speed up communication between layered chips, compared to planar layout.[7] 3D ICs promise many significant benefits, including:

Footprint – More functionality fits into a small space. This extends Moore’s Law and enables a new generation of tiny but powerful devices.

Cost – Partitioning a large chip into multiple smaller dies with 3D stacking can improve the yield and reduce the fabrication cost if individual dies are tested separately.[8][9]

Heterogeneous integration – Circuit layers can be built with different processes, or even on different types of wafers. This means that components can be optimized to a much greater degree than if they were built together on a single wafer. Moreover, components with incompatible manufacturing could be combined in a single 3D IC.[10]

Shorter interconnect – The average wire length is reduced. Common figures reported by researchers are on the order of 10-15%, but this reduction mostly applies to longer interconnect, which may affect circuit delay by a greater amount. Given that 3D wires have much higher capacitance than conventional in-die wires, circuit delay may or may not improve.

Power – Keeping a signal on-chip can reduce its power consumption by 10-100 times.[11] Shorter wires also reduce power consumption by producing less parasitic capacitance.[12] Reducing the power budget leads to less heat generation, extended battery life, and lower cost of operation.

Design – The vertical dimension adds a higher order of connectivity and offers new design possibilities.

Circuit security – The stacked structure complicates attempts to reverse engineer the circuitry. Sensitive circuits may also be divided among the layers in such a way as to obscure the function of each layer.[13]

Bandwidth – 3D integration allows large numbers of vertical vias between the layers. This allows construction of wide bandwidth buses between functional blocks in different layers. A typical example would be a processor+memory 3D stack, with the cache memory stacked on top of the processor. This arrangement allows a bus much wider than the typical 128 or 256 bits between the cache and processor.[14] Wide buses in turn alleviate the memory wall problem.[15]

Challenges

Because this technology is new it carries new challenges, including:

Yield – Each extra manufacturing step adds a risk for defects. In order for 3D ICs to be commercially viable, defects could be repaired or tolerated, or defect density can be improved.[16]

Heat – Heat building up within the stack must be dissipated. This is an inevitable issue as electrical proximity coorrelates with thermal proximity. Specific thermal hotspots must be more carefully managed.

Design complexity – Taking full advantage of 3D integration requires sophisticated design techniques and new CAD tools.[17]

TSV-introduced overhead – TSVs are large compared to gates and impact floorplans. At the 45nm technology node, the area footprint of a 10μm x 10μm TSV is comparable to that of about 50 gates.[18] Furthermore, manufacturability demands landing pads and keep-out zones which further increase TSV area footprint. Depending on the technology choices, TSVs block some subset of layout resources.[18] Via-first TSVs are manufactured before metallization, thus occupy the device layer and result in placement obstacles. Via-last TSVs are manufactured after metallization and pass through the chip. Thus, they occupy both the device and metal layers, resulting in placement and routing obstacles. While the usage of TSVs is generally expected to reduce wirelength, this depends on the number of TSVs and their characteristics.[18] Also, the granularity of inter-die partitioning impacts wirelength. It typically decreases for moderate (blocks with 20-100 modules) and coarse (block-level partitioning) granularities, but increases for fine (gate-level partitioning) granularities.[18]

Testing – To achieve high overall yield and reduce costs, separate testing of independent dies is essential.[19][20] However, tight integration between adjacent active layers in 3D ICs entails a significant amount of interconnect between different sections of the same circuit module that were partitioned to different dies. Aside from the massive overhead introduced by required TSVs, sections of such a module, e.g., a multiplier, cannot be independently tested by conventional techniques. This particularly applies to timing-critical paths laid out in 3D.

Lack of standards – There are few standards for TSV-based 3D-IC design, manufacturing, and packaging, although this issue is being addressed.[21][22] In addition, there are many integration options being explored such as via-last, via-first, via-middle;[23] interposers[24] or direct bonding; etc.

Heterogeneous integration supply chain – In heterogeneously integrated systems, the delay of one part from one of the different parts suppliers delays the delivery of the whole product, and so delays the revenue for each of the 3D-IC part suppliers.

Lack of clearly defined ownership – It is unclear who should own the 3D-IC integration and packaging/assembly. It could be assembly houses like ASE or the product OEMs.

Design styles

Depending on partitioning granularity, different design styles can be distinguished. Gate-level integration faces multiple challenges and currently appears less practical than block-level integration.[25]

Gate-level integration – This style partitions standard cells between multiple dies. It promises wirelength reduction and great flexibility. However, wirelength reduction may be undermined unless modules of certain minimal size are preserved. On the other hand, its adverse effects include the massive number of necessary TSVs for interconnects. This design style requires 3D place-and-route tools, which are unavailable yet. Also, partitioning a design block across multiple dies implies that it cannot be fully tested before die stacking. After die stacking (post-bond testing), a single failed die can render several good dies unusable, undermining yield. This style also amplifies the impact of process variation, especially inter-die variation. In fact, a 3D layout may yield more poorly than the same circuit laid out in 2D, contrary to the original promise of 3D IC integration.[26] Furthermore, this design style requires to redesign available Intellectual Property, since existing IP blocks and EDA tools do not provision for 3D integration.

Block-level integration – This style assigns entire design blocks to separate dies. Design blocks subsume most of the netlist connectivity and are linked by a small number of global interconnects. Therefore, block-level integration promises to reduce TSV overhead. Sophisticated 3D systems combining heterogeneous dies require distinct manufacturing processes at different technology nodes for fast and low-power random logic, several memory types, analog and RF circuits, etc. Block-level integration, which allows separate and optimized manufacturing processes, thus appears crucial for 3D integration. Furthermore, this style might facilitate the transition from current 2D design towards 3D IC design. Basically, 3D-aware tools are only needed for partitioning and thermal analysis.[27] Separate dies will be designed using (adapted) 2D tools and 2D blocks. This is motivated by the broad availability of reliable IP blocks. It is more convenient to use available 2D IP blocks and to place the mandatory TSVs in the unoccupied space between blocks instead of redesigning IP blocks and embedding TSVs. Design-for-testability structures are a key component of IP blocks and can therefore be used to facilitate testing for 3D ICs. Also, critical paths can be mostly embedded within 2D blocks, which limits the impact of TSV and inter-die variation on manufacturing yield. Finally, modern chip design often requires last-minute engineering changes. Restricting the impact of such changes to single dies is essential to limit cost.

Simulators


IntSim is an open-source CAD tool to simulate 2D and 3D-ICs. It can be used for predicting 2D/3D chip power, die size, number of metal levels and optimal sizes of metal levels based on various technology and design parameters. Users can also study scaling trends, and use IntSim to optimize their chip designs.

References

  1. ^ S. Borkar, “3D integration for energy efficient system design,” in Proc. Design Autom. Conf., 2011, pp. 214–219.
  2. ^ B. Black, D. Nelson, C. Webb, and N. Samra, "3D Processing Technology and Its Impact on iA32 Microprocessors," in Proc. of Int. Conf. on Computer Design, pp. 316-318, 2004.
  3. ^ Seguin, Steve. "World's First Stacked 3D Processor Created". September 16, 2008. http://www.tomshardware.com/news/rochester-3d-processor,6369.html
  4. ^ Science Daily. "3-D Computer Processor: 'Rochester Cube' Points Way To More Powerful Chip Designs". September 17, 2008. http://www.sciencedaily.com/releases/2008/09/080915105733.htm
  5. ^ Real World Technologies. "3D Integration: A Revolution in Design". May 2, 2007. http://realworldtech.com/page.cfm?ArticleID=RWT050207213241&p=6
  6. ^ Developer, Shed. "3D Processors, Stacking Core". September 20, 2005. http://www.devhardware.com/c/a/Computer-Processors/3D-Processor-Technology/,
  7. ^ Developer, Shed. "3D Processors, Stacking Core". September 20, 2005. http://www.devhardware.com/c/a/Computer-Processors/3D-Processor-Technology/1/
  8. ^ Xiangyu Dong and Yuan Xie, "System-level Cost Analysis and Design Exploration for 3D ICs", Proc. of Asia and South Pacific Design Automation Conference, 2009, http://www.cse.psu.edu/~yuanxie/3d.html
  9. ^ "3D IC Technology Delivers The Total Package" http://electronicdesign.com/article/engineering-essentials/3d_ic_technology_delivers_the_total_package.aspx Electronic Design July 02, 2010
  10. ^ James J-Q Lu, Ken Rose, & Susan Vitkavage “3D Integration: Why, What, Who, When?” http://www.future-fab.com/documents.asp?d_ID=4396 Future Fab Intl. Volume 23, 2007
  11. ^ William J. Dally, “Future Directions for On-Chip Interconnection Networks” page 17, http://www.ece.ucdavis.edu/~ocin06/talks/dally.pdf Computer Systems Laboratory Stanford University, 2006
  12. ^ Johnson, R Colin. "3-D chip stacks standardized". July 10, 2008. http://www.eetimes.com/electronics-news/4077835/3-D-chip-stacks-standardized
  13. ^ "3D-ICs and Integrated Circuit Security" http://www.tezzaron.com/about/papers/3D-ICs_and_Integrated_Circuit_Security.pdf Tezzaron Semiconductor, 2008
  14. ^ Dong Hyuk Woo, Nak Hee Seong, Dean L. Lewis, and Hsien-Hsin S. Lee. "An Optimized 3D-Stacked Memory Architecture by Exploiting Excessive, High-Density TSV Bandwidth." In Proceedings of the 16th International Symposium on High-Performance Computer Architecture, pp.429-440, Bangalore, India, January, 2010.
  15. ^ "Predicting the Performance of a 3D Processor-Memory Chip Stack" Jacob, P., McDonald, J.F. et al.Design & Test of Computers, IEEE Volume 22, Issue 6, Nov.–Dec. 2005 Page(s):540–547
  16. ^ Robert Patti, "Impact of Wafer-Level 3D Stacking on the Yield of ICs" http://www.future-fab.com/documents.asp?d_ID=4415 Future Fab Intl. Volume 23, 2007
  17. ^ "EDA's big three unready for 3D chip packaging" http://www.eetasia.com/ART_8800485666_480300_NT_fcb98510.HTM EE Times Asia October 25, 2007
  18. ^ a b c d D. H. Kim, S. Mukhopadhyay, S. K. Lim, “Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs,” in Proc. of Int. Workshop Sys.-Level Interconn. Pred., 2009, pp. 85–92.
  19. ^ S. Borkar, “3D integration for energy efficient system design,” in Proc. Design Autom. Conf., 2011, pp. 214–219.
  20. ^ H.-H. S. Lee, K. Chakrabarty, “Test challenges for 3D integrated circuits,” Des. Test. Comput., vol. 26, no. 5, pp. 26–35, Sep 2009
  21. ^ "3-D chip stacks standardized" http://www.eetimes.com/electronics-news/4077835/3-D-chip-stacks-standardized EE Times November 7, 2008
  22. ^ "SEMI International Standards Program Forms 3D Stacked IC Standards Committee" http://www.semi.org/en/press/CTR_042145?id=highlights SEMI press release December 7, 2010
  23. ^ "ADVANCED PACKAGING: 3D TSV Technologies Scenarios: Via First or Via Last? 2010 report" http://www.i-micronews.com/reports/3D-TSV-Technologies-Scenarios-Via-or-Via-Last-2010-report/108/ Yole report, 2010
  24. ^ "Si, glass interposers for 3D packaging: analysts' takes" http://www.electroiq.com/index/display/packaging-article-display/3806393153/articles/advanced-packaging/packaging0/integration/tsv/2010/august/si_-glass_interposers.html Advanced Packaging August 10, 2010
  25. ^ J. Knechtel, I. L. Markov, J. Lienig, "Assembling 2D Blocks into 3D Chips," in Proc. of the Int. Symp. on Physical Design, pp. 81-88, 2011
  26. ^ S. Garg, D. Marculescu, “3D-GCP: An analytical model for the impact of process variations on the critical path delay distribution of 3D ICs,” in Proc. Int. Symp. Quality Electron. Des., 2009, pp. 147–155
  27. ^ L. K. Scheffer, “CAD implications of new interconnect technologies,” in Proc. Design Autom. Conf., 2007, pp. 576–581.

Further reading

External links

Potential applications

Early products

Associations

Selected press references



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