Ferroelectric RAM

Ferroelectric RAM (FeRAM or FRAM [FeRAM is the accepted generic acronym for ferroelectric random-access memory.] ) is a random access memory similar in construction to DRAM but uses a ferroelectric layer instead of a dielectric layer to achieve non-volatility. FeRAM is one of a growing number of alternative non-volatile memory technologies that offer the same functionality as Flash memory. FeRAM advantages over Flash include: lower power usage, faster write speed and a much greater maximum number (exceeding 10¹⁶ for 3.3 V devices) of write-erase cycles. FeRAM disadvantages are: much lower storage densities than Flash devices, storage capacity limitations and higher cost.

FeRAM is competitive in niche applications where its operating characteristics give it an advantage over Flash. Compared to its more modern competitors MRAM and PCM, FeRAM volume production at Fujitsu began in 1999. FeRAMs at 1 megabit density were available in high volume in 2006 from both Fujitsu and Ramtron. Simtek Corporation [http://www.simtek.com/] introduced the first first 256K monolithic nvSRAM in 1994, currently 4 megabit nvSRAM chips are available. Limited volume production of a 4 megabit MRAM began at Freescale Semiconductor in July 2006. Intel Corporation and STMicroelectronics began shipping prototype samples of 128 megabit PCM memory in February 2008 [http://www.storagenewsletter.com/news/miscellaneous/stm-intel-numonyx-alverstone-phase-change] . The first chip containing high-density and low-cost PMC memory was announced by ASU's Center for Applied Nanoionics in October 2007 to become available in 18 months [http://www.wired.com/gadgets/miscellaneous/news/2007/10/ion_memory] .

Development of FeRAM began in the late 1980s. Work was done in 1991 at NASA's Jet Propulsion Laboratory on improving methods of read out, including a novel method of non-destructive readout using pulses of UV radiation. [ [http://trs-new.jpl.nasa.gov/dspace/bitstream/2014/33777/1/94-0506.pdf Optically Addressed Ferroelectric Memory with Non-Destructive Read-Out] ]

Much of the current FeRAM technology was developed by Ramtron a fabless semiconductor company. One major licensee is Fujitsu, who operate what is probably the largest semiconductor foundry production line with FeRAM capability. Since 1999 they have been using this line to produce standalone FeRAMs, as well as specialized chips (e.g. chips for smart cards) with embedded FeRAMs within. Fujitsu produces devices for Ramtron. Since at least 2001 Texas Instruments has collaborated with Ramtron to develop FeRAM test chips in a modified 130 nm process. In the fall of 2005 Ramtron reported that they were evaluating prototype samples of an 8 megabit FeRAM manufactured using Texas Instruments' FeRAM process. Fujitsu and Seiko-Epson were in 2005 collaborating in the development of a 180 nm FeRAM process. FeRAM research projects have also been reported at Samsung, Matsushita, Oki, Toshiba, Infineon, Hynix, Symetrix, Cambridge University, University of Toronto and the Interuniversity Microelectronics Centre (IMEC, Belgium).

Description

Conventional DRAM consists of a grid of small capacitors and their associated wiring and signaling transistors. Each storage element, a "cell", consists of one capacitor and one transistor, a so-called "1T-1C" device. DRAM cells scale directly with the size of the semiconductor fabrication process being used to make it. For instance, on the 90 nm process used by most memory providers to make DDR2 DRAM, the cell size is 0.22 μm², which includes the capacitor, transistor, wiring, and some amount of "blank space" between the various parts – it appears 35% utilization is typical, leaving 65% of the space wasted.

Data in a DRAM is stored as the presence or lack of an electrical charge in the capacitor, with the lack of charge generally representing "0". Writing is accomplished by activating the associated control transistor, draining the cell to write a "0", or sending current into it from a supply line if the new value should be "1". Reading is similar in nature; the transistor is again activated, draining the charge to a "sense amplifier". If a pulse of charge is noticed in the amplifier the cell held a charge and thus reads "1", the lack of such a pulse indicates a "0". Note that this process is "destructive", once the cell has been read, if it did hold a "1" it must be re-charged to that value again. Since a cell loses its charge after some time due to leak currents, it needs to be actively refreshed at intervals.

The 1T-1C storage cell design in an FeRAM is similar in construction to the storage cell in widely used DRAM in that both cell types include one capacitor and one access transistor. In a DRAM cell capacitor a linear dielectric is used whereas in an FeRAM cell capacitor the dielectric structure includes ferroelectric material, typically lead zirconate titanate (PZT).

A ferroelectric material has a nonlinear relationship between the applied electric field and the apparent stored charge. Specifically, the ferroelectric characteristic has the form of a hysteresis loop, which is very similar in shape to the hysteresis loop of ferromagnetic materials. The dielectric constant of a ferroelectric is typically much higher than that of a linear dielectric because of the effects of semi-permanent electric dipoles formed in the crystal structure of the ferroelectric material. When an external electric field is applied across a dielectric, the dipoles tend to align themselves with the field direction, produced by small shifts in the positions of atoms and shifts in the distributions of electronic charge in the crystal structure. After the charge is removed, the dipoles retain their polarization state. Typically binary "0"s and "1"s are stored as one of two possible electric polarizations in each data storage cell. For example, in the figure a "1" is encoded using the negative remnant polarization "-Pr", and a "0" is encoded using the positive remnant polarization "+Pr".

Operationally FeRAM is similar to DRAM. Writing is accomplished by applying a field across the ferroelectric layer by charging the plates on either side of it, forcing the atoms inside into the "up" or "down" orientation (depending on the polarity of the charge), thereby storing a "1" or "0". Reading, however, is somewhat different than in DRAM. The transistor forces the cell into a particular state, say "0". If the cell already held a "0", nothing will happen in the output lines. If the cell held a "1", the re-orientation of the atoms in the film will cause a brief pulse of current in the output as they push electrons out of the metal on the "down" side. The presence of this pulse means the cell held a "1". Since this process overwrites the cell, reading FeRAM is a destructive process, and requires the cell to be re-written if it was changed.

Generally the operation of FeRAM is similar to ferrite core memory, one of the primary forms of computer memory in the 1960s. Besides, the ferroelectric effect used in FeRAM was discovered in 1920. In comparison, FeRAM requires far less power to flip the state of the polarity, and does so much faster.

Comparison with other systems

Density

The main determinant of a memory system's cost is the density of the components used to make it up. Smaller components, and less of them, means that more cells can be packed onto a single chip, which in turn means more can be produced at once from a single silicon wafer. This improves yield, which is directly related to cost.

The lower limit to this scaling process is an important point of comparison, generally the technology that scales to the smallest cell size will end up being the least expensive per bit. FeRAM and DRAM are constructionally similar, and can generally be built on similar lines at similar sizes. In both cases the lower limit seems to be defined by the amount of charge needed to trigger the sense amplifiers. For DRAM this appears to be a problem at around 55 nm, at which point the charge stored in the capacitor is too small to be detected. It is not clear if FeRAM can scale to the same size, as the charge density of the PZT layer may not be the same as the metal plates in a normal capacitor.

An additional limitation on size is that materials tend to stop being ferroelectric when they are too small. [http://www.materials.drexel.edu/mml/pubs/Spanier_Kolpak_etal_NL06.pdf Ferroelectric Phase Transition in Individual Single-Crystalline BaTiO3 Nanowires] . See also the associated [http://www.physorg.com/news66555256.html press release] .] [Junquera and Ghosez, "Nature", 2003, [http://dx.doi.org/10.1038/nature01501 DOI 10.1038/nature01501] ] (This effect is related to the ferroelectric's "depolarization field".) There is ongoing research on addressing the problem of stabilizing ferroelectric materials; one approach, for example, uses molecular adsorbates.

To date, the commercial FeRAM devices have been produced at 350 nm and 130 nm. Early models required two FeRAM cells per bit, leading to very low densities, but this limitation has since been removed.

Power consumption

The key advantage to FeRAM over DRAM is what happens "between" the read and write cycles. In DRAM, the charge deposited on the metal plates leaks across the insulating layer and the control transistor, and disappears. In order for a DRAM to store data for anything other than a microscopic time, every cell must be periodically read and then re-written, a process known as "refresh". Each cell must be refreshed many times every second (~65 ms [ [http://download.micron.com/pdf/technotes/ddr2/TN4716.pdf TN-47-16: Designing for High-Density DDR2 Memory ] ] ) and this requires a continuous supply of power.

In contrast, FeRAM only requires power when actually reading or writing a cell. The vast majority of power used in DRAM is used for refresh, so it seems reasonable to suggest that the benchmark quoted by TTR-MRAM researchers is useful here too, indicating power usage about 99% lower than DRAM.

Another non-volatile memory type is Flash RAM, and like FeRAM it does not require a refresh process. Flash works by pushing electrons across a high-quality insulating barrier where they get "stuck" on one terminal of a transistor. This process requires high voltages, which are built up in a charge pump over time. This means that FeRAM could be expected to be lower power than Flash, at least for writing, as the write power in FeRAM is only marginally higher than reading. For a "mostly-read" device the difference might be slight, but for devices with more balanced read and write the difference could be expected to be much higher.

peed

DRAM speed is limited by the speed at which the current stored in the cells can be drained (for reading) or stored (for writing). Generally this ends up being defined by the capability of the control transistors, the capacitance of the lines carrying power to the cells, and the heat that power generates.

FeRAM is based on the physical movement of atoms in response to an external field, which happens to be extremely fast, settling in about 1 ns. In theory, this means that FeRAM could be much faster than DRAM. However, since power has to flow into the cell for reading and writing, the electrical and switching delays would likely be similar to DRAM overall. It does seem reasonable to suggest that FeRAM would require less charge than DRAM, because DRAMs need to "hold" the charge, whereas FeRAM would have been written to before the charge would have drained. That said, there is a delay in writing because the charge has to flow through the control transistor, which limits current somewhat.

In comparison to Flash the advantages are much more obvious. Whereas the read operation is likely to be similar in performance, the charge pump used for writing requires a considerable time to "build up" power, a process that FeRAM does not need. Flash memories commonly need about 1 ms to write a bit, whereas even current FeRAMs are at least 100 times that speed.

The theoretical performance of FeRAM is not entirely clear. Existing 350 nm devices have read times on the order of 50 to 60 ns. Although slow compared to modern DRAMs, which can be found with times on the order of 2 ns, common 350 nm DRAMs operated with a read time of about 35 ns, [ [http://ieeexplore.ieee.org/Xplore/login.jsp?url=/iel2/662/5918/00229238.pdf?tp=&arnumber=229238&isnumber=5918 IEEE Xplore - Login ] ] so FeRAM performance appears to be comparable given the same fab.

Overall

FeRAM remains a relatively small part of the overall semiconductor market. In 2005 worldwide semiconductor sales were US $235 billion (according to the Gartner Group), with the flash memory market accounting for US $18.6 billion (according to IC Insights).Fact|date=March 2007 The 2005 annual sales of Ramtron, perhaps the largest FeRAM vendor, were reported to be US $32.7 million. Flash memory is currently the overwhelmingly dominant NVRAM technology, and this situation seems likely to continue for at least the rest of the decade. The much larger sales of flash memory compared to the alternative NVRAMs support a much larger research and development effort. Flash memory is produced using semiconductor linewidths of 30 nm at Samsung (2007) while FeRAMs are produced in linewidths of 350 nm at Fujitsu and 130 nm at Texas Instruments (2007). Flash memory cells can store multiple bits per cell (currently 2 in the highest density NAND flash devices), and the number of bits per flash cell is projected to increase to 4 or even to 8 as a result of innovations in flash cell design. The areal bit densities of flash memory are consequently much higher than FeRAM, and thus the cost per bit of flash memory is orders of magnitude cheaper than FeRAM.

The density of FeRAM arrays might be increased by improvements in FeRAM foundry process technology and cell structures, such as the development of vertical capacitor structures (in the same way as DRAM) to reduce the area of the cell footprint. However, reducing the cell size may cause the data signal to become to too weak to be detectable. Both the existing and new markets for FeRAM need to be exploited to support increased levels of research and development spending. In its 2005 annual meeting Ramtron reported significant sales of its FeRAM products in a variety of sectors including (but not limited to) electronic metering, automotive (e.g. black boxes, smart air bags), business machines (e.g. printers, RAID disk controllers), instrumentation, medical equipment, industrial microcontrollers, and radio frequency identification tags. Ramtron's product mix might not be representative of the overall FeRAM market; however, its sales numbers give a useful indication of the wide variety of possible applications of FeRAM. The other emerging NVRAMs, such as MRAM, may seek to enter similar niche markets in competition with FeRAM. According to Gartner, the flash memory market grew at an annual rate of 20% in 2005. Judging from Ramtron's released sales numbers, in 2005 the FeRAM market was probably growing at least as fast as the flash memory market and probably faster. The company is projecting annual sales growth in the range of from 30 to 35% in 2006 and 2007 across its diversified FeRAM product line.

Theoretically, it should be possible to embed FeRAM cells using two additional masking steps during conventional CMOS semiconductor manufactureFact|date=December 2007. Flash typically requires nine masks. This could make possible for example, the integration of FeRAM on microcontrollers, where a simplified process would reduce costs. However, the materials used to make FeRAMs are not commonly used in CMOS integrated circuit manufacturing. Both the PZT ferroelectric layer and the noble metals used for electrodes raise CMOS process compatibility and contamination issues.

References

See also

*MRAM
*nvSRAM
*Phase-change memory
*Programmable metallization cell
*Memristor
*Racetrack memory
*Flash memory
*Ferroelectricity
*lead zirconate titanate
*Black box (disambiguation)#transportation

External links

* [http://www.fujitsu.com/global/services/microelectronics/technical/fram/ FRAM overview by Fujitsu]
* [http://www.eecg.toronto.edu/~ali/ferro/tutorial.html FeRAM Tutorial by the Department of Electrical and Computer Engineering at the University of Toronto]