- Flash memory
Computer memory types Volatile Non-volatile
Flash memory is a non-volatile computer storage chip that can be electrically erased and reprogrammed. It was developed from EEPROM (electrically erasable programmable read-only memory) and must be erased in fairly large blocks before these can be rewritten with new data. The high density NAND type must also be programmed and read in (smaller) blocks, or pages, while the NOR type allows a single machine word (byte) to be written and/or read independently.
The NAND type is primarily used in memory cards, USB flash drives, solid-state drives, and similar products, for general storage and transfer of data. The NOR type, which allows true random access and therefore direct code execution, is used as a replacement for the older EPROM and as an alternative to certain kinds of ROM applications. However, NOR flash memory may emulate ROM primarily at the machine code level; many digital designs need ROM (or PLA) structures for other uses, often at significantly higher speeds than (economical) flash memory may achieve. NAND or NOR flash memory is also often used to store configuration data in numerous digital products, a task previously made possible by EEPROMs or battery-powered static RAM.
Example applications of both types of flash memory include personal computers, PDAs, digital audio players, digital cameras, mobile phones, synthesizers, video games, scientific instrumentation, industrial robotics, medical electronics, and so on. In addition to being non-volatile, flash memory offers fast read access times, as fast as dynamic RAM, although not as fast as static RAM or ROM. Its mechanic shock resistance explain the popularity over hard disks in portable devices; so does its high durability, being able to withstand high pressure, temperature, immersion in water etc.
Although flash memory is technically a type of EEPROM, the term "EEPROM" is generally used to refer specifically to non-flash EEPROM which is erasable in small blocks, typically bytes. Because erase cycles are slow, the large block sizes used in flash memory erasing give it a significant speed advantage over old-style EEPROM when writing large amounts of data. Flash memory now costs far less than byte-programmable EEPROM and has become the dominant memory type wherever a significant amount of non-volatile, solid state storage is needed.
Flash memory (both NOR and NAND types) was invented by Dr. Fujio Masuoka while working for Toshiba circa 1980. According to Toshiba, the name "flash" was suggested by Dr. Masuoka's colleague, Mr. Shōji Ariizumi, because the erasure process of the memory contents reminded him of the flash of a camera. Dr. Masuoka presented the invention at the IEEE 1984 International Electron Devices Meeting (IEDM) held in San Francisco, California.
Intel Corporation saw the massive potential of the invention and introduced the first commercial NOR type flash chip in 1988. NOR-based flash has long erase and write times, but provides full address and data buses, allowing random access to any memory location. This makes it a suitable replacement for older read-only memory (ROM) chips, which are used to store program code that rarely needs to be updated, such as a computer's BIOS or the firmware of set-top boxes. Its endurance is 10,000 to 1,000,000 erase cycles. NOR-based flash was the basis of early flash-based removable media; CompactFlash was originally based on it, though later cards moved to less expensive NAND flash.
Toshiba announced NAND flash at the 1987 International Electron Devices Meeting. It has reduced erase and write times, and requires less chip area per cell, thus allowing greater storage density and lower cost per bit than NOR flash; it also has up to ten times the endurance of NOR flash. However, the I/O interface of NAND flash does not provide a random-access external address bus. Rather, data must be read on a block-wise basis, with typical block sizes of hundreds to thousands of bits. This made NAND flash unsuitable as a drop-in replacement for program ROM since most microprocessors and microcontrollers required byte-level random access. In this regard NAND flash is similar to other secondary data storage devices such as hard disks and optical media, and is thus very suitable for use in mass-storage devices such as memory cards. The first NAND-based removable media format was SmartMedia in 1995, and many others have followed, including MultiMediaCard, Secure Digital, Memory Stick and xD-Picture Card. A new generation of memory card formats, including RS-MMC, miniSD and microSD, and Intelligent Stick, feature extremely small form factors. For example, the microSD card has an area of just over 1.5 cm2, with a thickness of less than 1 mm. microSD capacities range from 64 MB to 64 GB, as of May 2011.
Principles of operation
Flash memory stores information in an array of memory cells made from floating-gate transistors. In traditional single-level cell (SLC) devices, each cell stores only one bit of information. Some newer flash memory, known as multi-level cell (MLC) devices, can store more than one bit per cell by choosing between multiple levels of electrical charge to apply to the floating gates of its cells.
In flash memory, each memory cell resembles a standard MOSFET, except the transistor has two gates instead of one. On top is the control gate (CG), as in other MOS transistors, but below this there is a floating gate (FG) insulated all around by an oxide layer. The FG is interposed between the CG and the MOSFET channel. Because the FG is electrically isolated by its insulating layer, any electrons placed on it are trapped there and, under normal conditions, will not discharge for many years. When the FG holds a charge, it screens (partially cancels) the electric field from the CG, which modifies the threshold voltage (VT) of the cell. During read-out, a voltage intermediate between the possible threshold voltages is applied to the CG, and the MOSFET channel will become conducting or remain insulating, depending on the VT of the cell, which is in turn controlled by charge on the FG. The current flow through the MOSFET channel is sensed and forms a binary code, reproducing the stored data. In a multi-level cell device, which stores more than one bit per cell, the amount of current flow is sensed (rather than simply its presence or absence), in order to determine more precisely the level of charge on the FG.
In NOR gate flash, each cell has one end connected directly to ground, and the other end connected directly to a bit line.
This arrangement is called "NOR flash" because it acts like a NOR gate: when one of the word lines is brought high, the corresponding storage transistor acts to pull the output bit line low. NOR Flash continues to be the technology of choice for embedded applications requiring a discrete non-volatile memory device. The low read latencies characteristic of NOR devices allow for both direct code execution and data storage in a single memory product. 
A single-level NOR flash cell in its default state is logically equivalent to a binary "1" value, because current will flow through the channel under application of an appropriate voltage to the control gate. A NOR flash cell can be programmed, or set to a binary "0" value, by the following procedure:
- an elevated on-voltage (typically >5 V) is applied to the CG
- the channel is now turned on, so electrons can flow from the source to the drain (assuming an NMOS transistor)
- the source-drain current is sufficiently high to cause some high energy electrons to jump through the insulating layer onto the FG, via a process called hot-electron injection
To erase a NOR flash cell (resetting it to the "1" state), a large voltage of the opposite polarity is applied between the CG and source, pulling the electrons off the FG through quantum tunneling. Modern NOR flash memory chips are divided into erase segments (often called blocks or sectors). The erase operation can only be performed on a block-wise basis; all the cells in an erase segment must be erased together. Programming of NOR cells, however, can generally be performed one byte or word at a time.
Internal charge pumps
Despite the need for high programming and erasing voltages, virtually all flash chips today require only a single supply voltage, and produce the high voltages via on-chip charge pumps.
NAND flash also uses floating-gate transistors, but they are connected in a way that resembles a NAND gate: several transistors are connected in series, and only if all word lines are pulled high (above the transistors' VT) is the bit line pulled low. These groups are then connected via some additional transistors to a NOR-style bit line array.
To read, most of the word lines are pulled up above the VT of a programmed bit, while one of them is pulled up to just over the VT of an erased bit. The series group will conduct (and pull the bit line low) if the selected bit has not been programmed.
Despite the additional transistors, the reduction in ground wires and bit lines allows a denser layout and greater storage capacity per chip. In addition, NAND flash is typically permitted to contain a certain number of faults (NOR flash, as is used for a BIOS ROM, is expected to be fault-free). Manufacturers try to maximize the amount of usable storage by shrinking the size of the transistor below the size where they can be made reliably, to the size where further reductions would increase the number of faults faster than it would increase the total storage available.
NAND flash uses tunnel injection for writing and tunnel release for erasing. NAND flash memory forms the core of the removable USB storage devices known as USB flash drives, as well as most memory card formats and solid-state drives available today.
One limitation of flash memory is that although it can be read or programmed a byte or a word at a time in a random access fashion, it can only be erased a "block" at a time. This generally sets all bits in the block to 1. Starting with a freshly erased block, any location within that block can be programmed. However, once a bit has been set to 0, only by erasing the entire block can it be changed back to 1. In other words, flash memory (specifically NOR flash) offers random-access read and programming operations, but cannot offer arbitrary random-access rewrite or erase operations. A location can, however, be rewritten as long as the new value's 0 bits are a superset of the over-written value's. For example, a nibble value may be erased to 1111, then written as 1110. Successive writes to that nibble can change it to 1010, then 0010, and finally 0000. Essentially, erasure sets (all) bits, and programming can only clear bits. Filesystems designed for flash devices can make use of this capability to represent sector metadata.
Although data structures in flash memory cannot be updated in completely general ways, this allows members to be "removed" by marking them as invalid. This technique may need to be modified for Multi-level Cell devices, where one memory cell holds more than one bit.
Common flash devices such as USB keys and memory cards provide only a block-level interface, or flash translation layer (FTL), which writes to a different cell each time to wear-level the device. This prevents incremental writing within a block, however it does help the device from being prematurely worn out by abusive and/or poorly designed hardware/software. For example, nearly all consumer devices ship formatted with MS-FAT file system, which pre-dates flash memory, having been designed for DOS, and disk media.
Another limitation is that flash memory has a finite number of program-erase cycles (typically written as P/E cycles). Most commercially available flash products are guaranteed to withstand around 100,000 P/E cycles, before the wear begins to deteriorate the integrity of the storage. Micron Technology and Sun Microsystems announced an SLC NAND flash memory chip rated for 1,000,000 P/E cycles on December 17, 2008.
The guaranteed cycle count may apply only to block zero (as is the case with TSOP NAND devices), or to all blocks (as in NOR). This effect is partially offset in some chip firmware or file system drivers by counting the writes and dynamically remapping blocks in order to spread write operations between sectors; this technique is called wear leveling. Another approach is to perform write verification and remapping to spare sectors in case of write failure, a technique called Bad Block Management (BBM). For portable consumer devices, these wearout management techniques typically extend the life of the flash memory beyond the life of the device itself, and some data loss may be acceptable in these applications. For high reliability data storage, however, it is not advisable to use flash memory that would have to go through a large number of programming cycles. This limitation is meaningless for 'read-only' applications such as thin clients and routers, which are only programmed once or at most a few times during their lifetimes.
The method used to read NAND flash memory can cause other cells near the cell being read to change over time if the surrounding cells of the block are not rewritten. This is generally in the hundreds of thousands of reads without a rewrite of those cells. The error does not appear when reading the original cell, but rather shows up when finally reading one of the surrounding cells. If the flash controller does not track the total number of reads across the whole storage device and rewrite the surrounding data periodically as a precaution, a read disturb error will likely occur with data loss as a result.
The low-level interface to flash memory chips differs from those of other memory types such as DRAM, ROM, and EEPROM, which support bit-alterability (both zero to one and one to zero) and random-access via externally accessible address buses.
While NOR memory provides an external address bus for read and program operations (and thus supports random-access); unlocking and erasing NOR memory must proceed on a block-by-block basis. With NAND flash memory, read and programming operations must be performed page-at-a-time while unlocking and erasing must happen in block-wise fashion.
Reading from NOR flash is similar to reading from random-access memory, provided the address and data bus are mapped correctly. Because of this, most microprocessors can use NOR flash memory as execute in place (XIP) memory, meaning that programs stored in NOR flash can be executed directly from the NOR flash without needing to be copied into RAM first. NOR flash may be programmed in a random-access manner similar to reading. Programming changes bits from a logical one to a zero. Bits that are already zero are left unchanged. Erasure must happen a block at a time, and resets all the bits in the erased block back to one. Typical block sizes are 64, 128, or 256 KB.
Bad block management is a relatively new feature in NOR chips. In older NOR devices not supporting bad block management, the software or device driver controlling the memory chip must correct for blocks that wear out, or the device will cease to work reliably.
The specific commands used to lock, unlock, program, or erase NOR memories differ for each manufacturer. To avoid needing unique driver software for every device made, a special set of Common Flash Memory Interface (CFI) commands allow the device to identify itself and its critical operating parameters.
Apart from being used as random-access ROM, NOR memories can also be used as storage devices by taking advantage of random-access programming. Some devices offer read-while-write functionality so that code continues to execute even while a program or erase operation is occurring in the background. For sequential data writes, NOR flash chips typically have slow write speeds compared with NAND flash.
NAND flash architecture was introduced by Toshiba in 1989. These memories are accessed much like block devices such as hard disks or memory cards. Each block consists of a number of pages. The pages are typically 512 or 2,048 or 4,096 bytes in size. Associated with each page are a few bytes (typically 1/32 of the data size) that can be used for storage of an error correcting code (ECC) checksum.
Typical block sizes include:
- 32 pages of 512+16 bytes each for a block size of 16 KB
- 64 pages of 2,048+64 bytes each for a block size of 128 KB
- 64 pages of 4,096+128 bytes each for a block size of 256 KB
- 128 pages of 4,096+128 bytes each for a block size of 512 KB.
While reading and programming is performed on a page basis, erasure can only be performed on a block basis. Number of Operations (NOPs) is the number of times the pages can be programmed. So far this number for MLC flash is always one whereas for SLC flash it is four.
NAND devices also require bad block management by the device driver software, or by a separate controller chip. SD cards, for example, include controller circuitry to perform bad block management and wear leveling. When a logical block is accessed by high-level software, it is mapped to a physical block by the device driver or controller. A number of blocks on the flash chip may be set aside for storing mapping tables to deal with bad blocks, or the system may simply check each block at power-up to create a bad block map in RAM. The overall memory capacity gradually shrinks as more blocks are marked as bad.
NAND relies on ECC to compensate for bits that may spontaneously fail during normal device operation. A typical ECC will correct a one bit error in each 2048 bits (256 bytes) using 22 bits of ECC code, or a one bit error in each 4096 bits (512 bytes) using 24 bits of ECC code. If ECC cannot correct the error during read, it may still detect the error. When doing erase or program operations, the device can detect blocks that fail to program or erase and mark them bad. The data is then written to a different, good block, and the bad block map is updated.
Most NAND devices are shipped from the factory with some bad blocks which are typically identified and marked according to a specified bad block marking strategy. By allowing some bad blocks, the manufacturers achieve far higher yields than would be possible if all blocks had to be verified good. This significantly reduces NAND flash costs and only slightly decreases the storage capacity of the parts.
When executing software from NAND memories, virtual memory strategies are often used: memory contents must first be paged or copied into memory-mapped RAM and executed there (leading to the common combination of NAND + RAM). A memory management unit (MMU) in the system is helpful, but this can also be accomplished with overlays. For this reason, some systems will use a combination of NOR and NAND memories, where a smaller NOR memory is used as software ROM and a larger NAND memory is partitioned with a file system for use as a non-volatile data storage area.
NAND is best suited to systems requiring high capacity data storage. This type of flash architecture offers higher densities and larger capacities at lower cost with faster erase, sequential write, and sequential read speeds, sacrificing the random-access and execute in place advantage of the NOR architecture.
A group called the Open NAND Flash Interface Working Group (ONFI) has developed a standardized low-level interface for NAND flash chips. This allows interoperability between conforming NAND devices from different vendors. The ONFI specification version 1.0 was released on December 28, 2006. It specifies:
- a standard physical interface (pinout) for NAND flash in TSOP-48, WSOP-48, LGA-52, and BGA-63 packages
- a standard command set for reading, writing, and erasing NAND flash chips
- a mechanism for self-identification (comparable to the Serial Presence Detection feature of SDRAM memory modules)
A group of vendors, including Intel, Dell, and Microsoft formed a Non-Volatile Memory Host Controller Interface (NVMHCI) Working Group. The goal of the group is to provide standard software and hardware programming interfaces for nonvolatile memory subsystems, including the "flash cache" device connected to the PCI Express bus.
Distinction between NOR and NAND flash
NOR and NAND flash differ in two important ways:
- the connections of the individual memory cells are different
- the interface provided for reading and writing the memory is different (NOR allows random-access for reading, NAND allows only page access)
These two are linked by the design choices made in the development of NAND flash. A goal of NAND flash development was to reduce the chip area required to implement a given capacity of flash memory, and thereby to reduce cost per bit and increase maximum chip capacity so that flash memory could compete with magnetic storage devices like hard disks.
NOR and NAND flash get their names from the structure of the interconnections between memory cells. In NOR flash, cells are connected in parallel to the bit lines, allowing cells to be read and programmed individually. The parallel connection of cells resembles the parallel connection of transistors in a CMOS NOR gate. In NAND flash, cells are connected in series, resembling a NAND gate. The series connections consume less space than parallel ones, reducing the cost of NAND flash. It does not, by itself, prevent NAND cells from being read and programmed individually.
When NOR flash was developed, it was envisioned as a more economical and conveniently rewritable ROM than contemporary EPROM and EEPROM memories. Thus random-access reading circuitry was necessary. However, it was expected that NOR flash ROM would be read much more often than written, so the write circuitry included was fairly slow and could only erase in a block-wise fashion. On the other hand, applications that use flash as a replacement for disk drives do not require word-level write address, which would only add to the complexity and cost unnecessarily.
Because of the series connection and removal of wordline contacts, a large grid of NAND flash memory cells will occupy perhaps only 60% of the area of equivalent NOR cells (assuming the same CMOS process resolution, e.g. 130nm, 90 nm, 65 nm). NAND flash's designers realized that the area of a NAND chip, and thus the cost, could be further reduced by removing the external address and data bus circuitry. Instead, external devices could communicate with NAND flash via sequential-accessed command and data registers, which would internally retrieve and output the necessary data. This design choice made random-access of NAND flash memory impossible, but the goal of NAND flash was to replace hard disks, not to replace ROMs.
The write endurance of SLC floating-gate NOR flash is typically equal to or greater than that of NAND flash, while MLC NOR and NAND flash have similar endurance capabilities. Example Endurance cycle ratings listed in datasheets for NAND and NOR flash are provided.
- SLC NAND flash is typically rated at about 100k cycles (Samsung OneNAND KFW4G16Q2M)
- MLC NAND flash used to be rated at about 5–10k cycles (Samsung K9G8G08U0M) but is now typically 1k - 3k cycles
- TLC NAND flash is typically rated at about 100-500 cycles
- SLC floating-gate NOR flash has typical endurance rating of 100k to 1M cycles (Numonyx M58BW 100k; Spansion S29CD016J 1,000k)
- MLC floating-gate NOR flash has typical endurance rating of 100k cycles (Numonyx J3 flash)
However, by applying certain algorithms and design paradigms such as wear leveling and memory over-provisioning, the endurance of a storage system can be tuned to serve specific requirements.
Flash file systems
Because of the particular characteristics of flash memory, it is best used with either a controller to perform wear leveling and error correction or specifically designed flash file systems, which spread writes over the media and deal with the long erase times of NOR flash blocks. The basic concept behind flash file systems is: When the flash store is to be updated, the file system will write a new copy of the changed data to a fresh block, remap the file pointers, then erase the old block later when it has time.
In practice, flash file systems are only used for memory technology devices (MTDs), which are embedded flash memories that do not have a controller. Removable flash memory cards and USB flash drives have built-in controllers to perform wear leveling and error correction so use of a specific flash file system does not add any benefit.
Multiple chips are often arrayed to achieve higher capacities for use in consumer electronic devices such as multimedia players or GPS. The capacity of flash chips generally follows Moore's Law because they are manufactured with many of the same integrated circuits techniques and equipment.
Consumer flash drives typically have sizes measured in powers of two (e.g., 512 MB, 8 GB). This includes SSDs as hard drive replacements, even though traditional hard drives tend to use decimal units. Thus, an SSD marked as "64 GB" is actually 64 × 1,0243 bytes (64 GiB). In reality, most users will have slightly less capacity than this available, due to the space taken by file system metadata.
In 2005, Toshiba and SanDisk developed a NAND flash chip capable of storing 1 GB of data using multi-level cell (MLC) technology, capable of storing two bits of data per cell. In September 2005, Samsung Electronics announced that it had developed the world’s first 2 GB chip.
In March 2006, Samsung announced flash hard drives with a capacity of 4 GB, essentially the same order of magnitude as smaller laptop hard drives, and in September 2006, Samsung announced an 8 GB chip produced using a 40-nm manufacturing process. In January 2008, Sandisk announced availability of their 16 GB MicroSDHC and 32 GB SDHC Plus cards.
In 2009, Kingston announced a 256 GB flash drive available only in the UK and other parts of Europe. As of 2010, however, it is available in the USA.
An PCI-e SSD with a maximum capacity of 5 TB was announced by Fusion-Io on November 17, 2009, as being capable of sustaining 6 GB per second transfer rate.
There are still flash-chips manufactured with capacities under or around 1 MB, e.g., for BIOS-ROMs and embedded applications.
NAND flash memory cards are much faster at reading than writing so it is the maximum read speed that is commonly advertised.
As a chip wears out, its erase/program operations slow down considerably, requiring more retries and bad block remapping. Transferring multiple small files, each smaller than the chip-specific block size, could lead to a much lower rate. Access latency also influences performance, but less so than with their hard drive counterpart.
The speed is sometimes quoted in MB/s (megabytes per second), or as a multiple of that of a legacy single speed CD-ROM, such as 60×, 100× or 150×. Here 1× is equivalent to 150 kB/s. For example, a 100× memory card gives 150 kB/s × 100 = 15,000 kB/s = 14.65 MB/s.
Performance also depends on the quality of memory controllers. Even when the only change to manufacturing is die-shrink, the absence of an appropriate controller can result in degraded speeds.
Serial flash is a small, low-power flash memory that uses a serial interface, typically SPI, for sequential data access. When incorporated into an embedded system, serial flash requires fewer wires on the PCB than parallel flash memories, since it transmits and receives data one bit at a time. This may permit a reduction in board space, power consumption, and total system cost.
There are several reasons why a serial device, with fewer external pins than a parallel device, can significantly reduce overall cost:
- Many ASICs are pad-limited, meaning that the size of the die is constrained by the number of wire bond pads, rather than the complexity and number of gates used for the device logic. Eliminating bond pads thus permits a more compact integrated circuit, on a smaller die; this increases the number of dies that may be fabricated on a wafer, and thus reduces the cost per die.
- Reducing the number of external pins also reduces assembly and packaging costs. A serial device may be packaged in a smaller and simpler package than a parallel device.
- Smaller and lower pin-count packages occupy less PCB area.
- Lower pin-count devices simplify PCB routing.
There are two major SPI flash types. The first type is characterized by small pages and one or more internal SRAM page buffers allowing a complete page to be read to the buffer, partially modified, and then written back (For example: The Atmel AT45 DataFlash™ or the Micron Technology Page Erase NOR Flash). The second type has larger sectors. The smallest sectors typically found in an SPI flash are 4 kB, but they can be as large as 64 kB. Since the SPI flash lacks an internal SRAM buffer, the complete page must be read out and modified before written back, making it slow to manage. SPI flash is cheaper than DataFlash and is therefore a good choice when the application is code shadowing.
The two types are not easily exchangeable, since they do not have the same pinout, and the command sets are incompatible.
With the increasing speed of modern CPUs, parallel flash devices are often much slower than the memory bus of the computer they are connected to. Conversely, modern SRAM offers access times below 10 ns, while DDR2 SDRAM offers access times below 20 ns. Because of this, it is often desirable to shadow code stored in flash into RAM; that is, the code is copied from flash into RAM before execution, so that the CPU may access it at full speed. Device firmware may be stored in a serial flash device, and then copied into SDRAM or SRAM when the device is powered-up. Using an external serial flash device rather than on-chip flash removes the need for significant process compromise (a process that is good for high speed logic is generally not good for flash and vice-versa). Once it is decided to read the firmware in as one big block it is common to add compression to allow a smaller flash chip to be used. Typical applications for serial flash include storing firmware for hard drives, Ethernet controllers, DSL modems, wireless network devices, etc.
Flash memory as a replacement for hard drives
One more recent application for flash memory is as a replacement for hard disks. Flash memory does not have the mechanical limitations and latencies of hard drives, so a solid-state drive (SSD) is attractive when considering speed, noise, power consumption, and reliability. Flash drives are gaining traction as mobile device secondary storage devices; they are also used as substitutes for hard drives in high-performance desktop computers and some servers with RAID and SAN architectures.
There remain some aspects of flash-based SSDs that make them unattractive. The cost per gigabyte of flash memory remains significantly higher than that of hard disks. Also flash memory has a finite number of P/E cycles, but this seems to be currently under control since warranties on flash-based SSDs are approaching those of current hard drives.
In June 2006, Samsung Electronics released the first flash-memory based PCs, the Q1-SSD and Q30-SSD, both of which used 32 GB SSDs, and were at least initially available only in South Korea. Dell Computer introduced a 32GB SSD option on its Latitude D420 and D620 ATG laptops in April 2007—at $549 more than a hard-drive equipped version.
At the Las Vegas CES 2007 Summit Taiwanese memory company A-DATA showcased flash memory based SSD units in capacities of 32 GB, 64 GB and 128 GB. The XO-1, developed by the One Laptop Per Child (OLPC) association, uses flash memory rather than a hard drive. As of March 2009, a Salt Lake City company called Fusion-io claims the fastest SSD with sequential read/write speeds of 1500 MB/1400 MB's per second.
There are also hybrid techniques such as hybrid drive and ReadyBoost that attempt to combine the advantages of both technologies, using flash as a high-speed non-volatile cache for files on the disk that are often referenced, but rarely modified, such as application and operating system executable files. Also, Addonics has a PCI adapter for four CF cards, creating a RAID-able array of solid-state storage that is much cheaper than the hardwired-chips PCI card kind.
Early versions of the ASUS Eee PC used a flash-based SSD of 2 GB to 20 GB, depending on model, although later versions of the machine use hard disks. The Apple Inc. Macbook Air notebooks have the option of a 256 GB Solid State hard drive. The Lenovo ThinkPad X300 also features a built-in 64 GB Solid State Drive.
Sharkoon has developed a device that uses six SDHC cards in RAID-0 configuration as an SSD. They claim users may use more affordable High-Speed 8 GB SDHC cards to get similar or better results than can be obtained from traditionally built SSDs at a lower cost.
One source states that, in 2008, the flash memory industry includes about US$9.1 billion in production and sales. Other sources put the flash memory market at a size of more than US$20 billion in 2006, accounting for more than eight percent of the overall semiconductor market and more than 34 percent of the total semiconductor memory market.
Due to its relatively simple structure and high demand for higher capacity, NAND flash memory is the most aggressively scaled technology among electronic devices. The heavy competition among the top few manufacturers only adds to the aggressiveness in shrinking the design rule or process technology node.Current projections show the technology to reach approximately 20 nm by around late 2011. While the expected shrink timeline is a factor of two every three years per original version of Moore's law, this has recently been accelerated in the case of NAND flash to a factor of two every two years.
As the feature size of flash memory cells reach the minimum limit (19 nm as of April 2011 ), further flash density increases will be driven by greater levels of MLC, possibly 3-D stacking of transistors, and improvements to the manufacturing process. The decrease in endurance and increase in uncorrectable bit error rates that accompany feature size shrinking can be compensated by improved error correction mechanisms. Even with these advances, it may be impossible to economically scale flash to smaller and smaller dimensions. Many promising new technologies (such as FeRAM, MRAM, PMC, PCM, and others) are under investigation and development as possible more scalable replacements for flash.
- List of flash file systems
- Secure USB drive
- Open NAND Flash Interface Working Group
- Write amplification
- ^ "Owners of QM2 seabed camera found". BBC News. 2010-02-11. http://news.bbc.co.uk/1/hi/england/8510314.stm.
- ^ Fulford, Benjamin (24 June 2002). "Unsung hero". Forbes. http://www.forbes.com/global/2002/0624/030.html. Retrieved 2008-03-18.
- ^ US 4531203 Fujio Masuoka
- ^ Tal, Arie (February 2002). "NAND vs. NOR flash technology: The designer should weigh the options when using flash memory". http://www2.electronicproducts.com/NAND_vs_NOR_flash_technology-article-FEBMSY1-FEB2002.aspx. Retrieved 2010-07-31.
- ^ "SanDisk ships 32GB mobile memory card". Computerworld. March 22, 2010. http://www.computerworld.com/s/article/9173879/SanDisk_ships_32GB_mobile_memory_card.
- ^ "PSoC Designer(TM) Device Selection Guide - AN2209": "... The PSoC ... utilizes a unique Flash process: SONOS"
- ^ Zitlaw, Cliff. "The Future of NOR Flash Memory". Memory Designline. UBM Media. http://www.eetimes.com/design/memory-design/4215634. Retrieved 3 May 2011.
- ^ Jonathan Thatcher, Fusion-io; Tom Coughlin, Coughlin Associates; Jim Handy, Objective-Analysis; Neal Ekker, Texas Memory Systems (April 2009) (pdf). NAND Flash Solid State Storage for the Enterprise, An In-depth Look at Reliability. Solid State Storage Initiative (SSSI) of the Storage Network Industry Association (SNIA). http://www.snia.org/forums/sssi/knowledge/education/SSSI_NAND_Reliability_White_Paper.pdf.
- ^ "Micron Collaborates with Sun Microsystems to Extend Lifespan of Flash-Based Storage, Achieves One Million Write Cycles" (Press release). Micron Technology, Inc.. 2008-12-17. http://investors.micron.com/releasedetail.cfm?ReleaseID=440650.
- ^ "TN-29-17: NAND Flash Design and Use Considerations Introduction". Micron. April 2010. http://download.micron.com/pdf/technotes/nand/tn2917.pdf. Retrieved 2011-07-29.
- ^ a b Kawamatus, Tatsuya. [techon.nikkeibp.co.jp/NEA/solutions/0808002.pdf "TECHNOLOGY FOR MANAGING NAND FLASH"]. Hagiwara sys-com co., LTD. techon.nikkeibp.co.jp/NEA/solutions/0808002.pdf. Retrieved 2011-08-01.
- ^ Kim, Jesung; Kim, John Min; Noh, Sam H.; Min, Sang Lyul; Cho, Yookun (2002-05). "A Space-Efficient Flash Translation Layer for CompactFlash Systems". Proceedings of the IEEE 48 (2): pp. 366–375. http://ieeexplore.ieee.org/iel5/30/21778/01010143.pdf?tp=&isnumber=&arnumber=1010143. Retrieved 2008-08-15.
- ^ TN-29-07: Small-Block vs. Large-Block NAND flash Devices Explains 512+16 and 2048+64-byte blocks
- ^ AN10860 LPC313x NAND flash data and bad block management Explains 4096+128-byte blocks.
- ^ Smith, Lance L. (2009-08-18). "NAND Flash Solid State Storage Performance and Capability -- an In-depth Look". SNIA. http://www.flashmemorysummit.com/English/Collaterals/Proceedings/2009/20090812_T1B_Smith.pdf. Retrieved 2010-06-17.
- ^ "Samsung ECC algorithm" (PDF). Samsung. 2008-06. http://www.elnec.com/sw/samsung_ecc_algorithm_for_256b.pdf. Retrieved 2008-08-15.
- ^ "Open NAND Flash Interface Specification" (PDF). Open NAND Flash Interface. 28 December 2006. http://onfi.org/wp-content/uploads/2009/02/onfi_1_0_gold.pdf. Retrieved 2010-07-31.
- ^ A list of ONFi members is available at http://onfi.org/membership/.
- ^ "Dell, Intel And Microsoft Join Forces To Increase Adoption Of NAND-Based Flash Memory In PC Platforms". REDMOND, Wash: Intel. May 30, 2007. http://www.intel.com/pressroom/archive/releases/20070530corp.htm. Retrieved 2008-11-30. [dead link]
- ^ See pages 5-7 of Toshiba's "NAND Applications Design Guide" under External links.
- ^ Pavan, Paolo; Bez, Roberto; Olivo, Piero; Zononi, Enrico (1997). "Flash Memory Cells — An Overview". Proceedings of the IEEE 85 (8): pp. 1248–1271. 1997-08. doi:10.1109/5.622505. http://ieeexplore.ieee.org/iel3/5/13533/00622505.pdf?tp=&isnumber=&arnumber=622505. Retrieved 2008-08-15.
- ^  Western Digital White Paper describing calculation and effects of SSD endurance
- ^ Shilov, Anton (September 12, 2005). "Samsung Unveils 2GB Flash Memory Chip". X-bit labs. http://www.xbitlabs.com/news/memory/display/20050912212649.html. Retrieved 2008-11-30.
- ^ Gruener, Wolfgang (September 11, 2006). "Samsung announces 40-nm Flash, predicts 20 nm devices". TG Daily. http://www.tgdaily.com/content/view/28504/135/. Retrieved 2008-11-30.
- ^ 12 GB MicroSDHC
- ^ 32 GB SDHC Plus
- ^ "Fusion-io Achieves One Terabyte per Second Sustained Bandwidth". November 17, 2009. http://www.fusionio.com/press/Fusion-io-Achieves-One-Terabyte-per-Second-Sustained-Bandwidth/. Retrieved 2011-07-26.
- ^ Samsung Confirms 32nm Flash Problems, Working on New SSD Controller
- ^ Many serial flash devices implement a bulk read mode and incorporate an internal address counter, so that it is trivial to configure them to transfer their entire contents to RAM on power-up. When clocked at 50 MHz, for example, a serial flash could transfer a 64 Mbit firmware image in less than two seconds.
- ^ Lyth0s (March 17, 2011). "SSD vs. HDD". elitepcbuilding.com. http://elitepcbuilding.com/ssd-vs-hdd. Retrieved July 11, 2011.
- ^ "Flash Solid State Disks - Inferior Technology or Closet Superstar?". STORAGEsearch. http://www.storagesearch.com/bitmicro-art1.html. Retrieved 2008-11-30.
- ^ "Samsung Electronics Launches the World’s First PCs with NAND Flash-based Solid State Disk". Press Release. Samsung. May 24, 2006. http://www.samsung.com/he/presscenter/pressrelease/pressrelease_20060524_0000257996.asp. Retrieved 2008-11-30.
- ^ "Dell joins the fray, offers SSD in Latitude D420, D620". Engadget. April 24, 2007. http://www.engadget.com/2007/04/24/dell-joins-the-fray-offers-ssd-in-latitude-d420-d620/. Retrieved 2009-10-27.
- ^ Valich, Theo (January 10, 2007). "Future of Flash revealed". http://www.theinquirer.net/default.aspx?article=36841. Retrieved July 11, 2011.
- ^ "Fusion-io Announces the ioDrive Duo - The World's Fastest and Most Innovative SSD". Fusion-io. http://www.fusionio.com/press/Fusion-io-Announces-the-ioDrive-Duo-The-World-s-Fastest-and-Most-Innovative-SSD/. Retrieved July 11, 2011.
- ^ "Addonics PCI adapter for 4 CF cards". http://www.addonics.com/products/flash_memory_reader/ad4cfprj.asp.
- ^ Yinug, Christopher Falan (July 2007). "The Rise of the Flash Memory Market: Its Impact on Firm Behavior and Global Semiconductor Trade Patterns" (PDF). Journal of International Commerce and Economics. Archived from the original on 2008-05-29. http://web.archive.org/web/20080529180622/http://www.usitc.gov/journal/Final_falan_article1.pdf. Retrieved 2008-04-19.
- ^ Curtis Ray, Austin (April 21, 2011). "SanDisk Announces 19nm Memory Chip". Maximum PC. http://www.maximumpc.com/article/news/sandisk_announces_19nm_memory_chip. Retrieved 2011-4-21.
- ^ Lal Shimpi, Anand (December 2, 2010). "Micron's ClearNAND: 25nm + ECC, Combats Increasing Error Rates". Anandtech. http://www.anandtech.com/show/4043/micron-announces-clearnand-25nm-with-ecc. Retrieved 2010-12-02.
- ^ Kim, Kinam; Koh, Gwan-Hyeob (2004-05-16). Future Memory Technology including Emerging New Memories. Serbia and Montenegro: Proceedings of the 24th International Conference on Microelectronics (published 2004-05). pp. 377–384. http://ieeexplore.ieee.org/iel5/9193/29143/01314646.pdf?tp=&isnumber=&arnumber=1314646. Retrieved 2008-08-15.
- New Pulse Measurement System For Semiconductor Device Characterization
- Semiconductor Characterization System has diverse functions
- NAND Flash Applications Design Guide by Toshiba, April 2003 v. 1.0
- Understanding and selecting higher performance NAND architectures
Solid-state drives Key terminology Flash manufacturers Controllers Independent Captive SSD ManufacturersList of solid-state drive manufacturers Interfaces Related organizations
Wikimedia Foundation. 2010.