Threshold voltage

The threshold voltage of a MOSFET is usually defined as the gate voltage where an inversion layer forms at the interface between the insulating layer (oxide) and the substrate (body) of the transistor. The creation of this layer is described next.

In an n-MOSFET the substrate of the transistor is composed of p-type silicon (see doping (semiconductor)), which has positively charged mobile holes as carriers. When a positive voltage is applied on the gate, an electric field causes the holes to be repelled from the interface, creating a depletion region containing immobile negatively charged acceptor ions. A further increase in the gate voltage eventually causes electrons to appear at the interface, in what is called an inversion layer, or channel. Historically the gate voltage at which the electron density at the interface is the same as the hole density in the neutral bulk material is called the threshold voltage. Practically speaking the threshold voltage is the voltage at which there are sufficient electrons in the inversion layer to make a low resistance conducting path between the MOSFET source and drain.

In the figures, the source and drain are labeled "n⁺" to indicate heavily doped n-regions. The depletion layer dopant is labeled "N_A^-" to indicate that the ions in the depletion layer are negatively charged and there are very few holes. In the bulk the number of holes "p = N_A" making the bulk charge neutral.

If the gate voltage is below the threshold voltage, the transistor is turned off and ideally there is no current from the drain to the source of the transistor. In fact, there is a current even for gate biases below threshold (subthreshold leakage) current, although it is small and varies exponentially with gate bias.

If the gate voltage is above the threshold voltage, the transistor is turned on, due to there being many electrons in the channel at the oxide-silicon interface, creating a low-resistance channel where charge can flow from drain to source. For voltages significantly above threshold, this situation is called strong inversion. The channel is tapered when "V_D > 0" because the voltage drop due to the current in the resistive channel reduces the oxide field supporting the channel as the drain is approached.

In modern devices the threshold voltage is a much less clear-cut parameter subject to variation with the biases applied to the device; see drain induced barrier lowering.

Body effect

The body effect describes the changes in the threshold voltage by the change in $V\_\{SB\}$, the source-bulk voltage. Since the body influences the threshold voltage (when it is not tied to the source), it can be thought of as a second gate, and is sometimes referred to as the "back gate"; the body effect is sometimes called the "back-gate effect". [ Marco Delaurenti, PhD dissertation, "Design and optimization techniques of high-speed VLSI circuits" (1999)) [http://equars.com/~marco/poli/phd/node20.html] ]

For an enhancement mode, n-mos MOSFET body effect upon threshold voltage is computed according to the Shichman-Hodges model [ NanoDotTek Report NDT14-08-2007, 12 August 2007 [http://www.nanodottek.com/NDT14_08_2007.pdf] ] (accurate for very old technology) using the following equation.

::$V\_\{TN\}\; =\; V\_\{TO\}\; +\; gamma\; (sqrt\{V\_\{SB\}\; +\; 2phi\_F\}\; -\; sqrt\{2phi\_F\})$

where $V\_\{TN\}$ is the threshold voltage when substrate bias is present, $V\_\{SB\}$ is the source-to-body substrate bias, $2phi\_F$ is the surface potential, and $V\_\{TO\}$ is threshold voltage for zero substrate bias, $gamma\; =\; (t\_\{ox\}/epsilon\_\{ox\})sqrt\{2qepsilon\_\{si\}N\_A\}$ is the body effect parameter, $t\_\{ox\}$ is oxide thickness, $epsilon\_\{ox\}$ is oxide permitivity, $epsilon\_\{si\}$ is the permitivity of silicon, $N\_A$ is a doping concentration, $q$ is the charge of an electron.

Dependence on oxide thickness

In a given technology node such as the 90 nanometer CMOS process threshold voltage depends on the choice of oxide and on oxide thickness. Using the body formulas above $V\_\{TN\}$ is directly proportional to $gamma$ and $t\_\{OX\}$ which is the parameter for oxide thickness.

Thus the lower the oxide thickness, the lower the threshold voltage. While this may seem to be a design gain, it is not without cost, the lower the oxide thickness the higher the subthreshold leakage current through the device will be. The design specification for 90 nanometer was set at 1 nanometers for this reason. [ Sugii, Watanabe and Sugatani. "Transistor Design for 90-nm Generation and Beyond." (2002) [http://www.xilinx.com/support/documentation/white_papers/wp221.pdf] ] This kind of tunneling, called Fowler-nordheim Tunneling [ S. M. Sze, "Physics of Semicinductor Devices", Second Edition, New York: Wiley and Sons, 1981, pp. 496–504.] .

::$I\_\{fn\}\; =\; C\_1WL(E\_\{ox\})^2e^\{-E\_0/E\_\{ox$where $C\_1$ and $E\_0$ are constants and $E\_\{ox\}$ is the electric field across the gate oxide.

Before 90 nanometers, a dual oxide approach for oxide thickness was common industry standard solution to this issue. With a 90 nanometer process technology, a triple oxide approach has been adopted in some cases [ Anil Telikepalli, Xilinx Inc, "Power considerations in designing with 90 nm FPGAs" (2005)) [http://www.pldesignline.com/showArticle.jhtml?articleID=174402265/] ] . One standard thin oxide for most transistors, another for I/O driver cells, and a third for memory and pass transistor cells. These differences are based purely on the characteristics of oxide thickness on threshold voltage of CMOS technologies.

Dependence on temperature

As with the case of oxide thickness affecting threshold voltage, Temperature has an effect on the threshold voltage of a CMOS device. Expanding on part of the equation in the body effect section

::$phi\_f\; =\; (kT/q)\; ln\{(N\_A/N\_i)\}$

where $k$ is Boltzmann's constant, $T$ is Temperature, $q$ is the charge of an electron, $N\_A$ is a doping parameter and $N\_i$ is the intrinsic doping parameter for the substrate.

We see that the surface potential has a direct relationship with the temperature. Looking above, that while the threshold voltage does not have a direct relationship but is not independent of the effects. On average this variation is between -4mV/°C and -2mV/°C depending on doping level [Weste and Eshraghian, "Principles of CMOS VLSI Design : a systems perspective", Second Edition, (1993) pp.48 ISBN 0-201-53376-6] . For a change of 30 °C this results in significant variation from the 500mV design parameter commonly used for the 90 nanometer technology node.

References

ee also

*MOSFET operation
*Channel length modulation
*Drain-induced barrier lowering