Serial Peripheral Interface Bus

Protocol Analyzers

SPI Protocol Analyzers are tools which sample an SPI bus and decode the electrical signals to provide a higher level view of the data been transmitted on the bus. Some SPI protocol analyzers are built into oscilloscopes while others are stand-alone devices.

Related Terms

Queued Serial Peripheral Interface (QSPI)

The queued serial peripheral interface (QSPI) is one type of SPI controller, not another bus type. It uses a data queue with programmable queue pointers that allow some data transfers without CPU intervention [ [http://www.freescale.com/files/microcontrollers/doc/ref_manual/QSMRM.pdf Queued Serial Module Reference Manual] , Freescale Semiconductor] . It also has a wrap-around mode that allows continuous transfers to and from the queue with no CPU intervention. As a result, the peripherals appear to the CPU as memory-mapped parallel devices. This feature is useful in applications such as control of an A/D converter. Other programmable features in QSPI are chip selects and transfer length/delay.

SPI controllers from different vendors support different feature sets; such DMA queues are not uncommon, although they may be associated with separate DMA engines rather than the SPI controller itself. Most SPI master controllers integrate support for up to four chipselects, although some require chipselects to be managed separately through GPIO lines.

Microwire

Microwire is essentially a predecessor of SPI. It's a strict subset: half duplex, and using SPI mode 0. (Microwire-Plus supports other SPI modes.) Microwire chips tend to need slower clock rates than newer SPI versions; perhaps 2 MHz vs 20 MHz. Some Microwire chips also support a 3-Wire mode (see below), which fits neatly with the restriction to half duplex.

3-Wire Serial Buses

As mentioned above, one variant of SPI uses single bidirectional data line (Slave Out/Slave IN, called SISO) instead of two unidirectional ones (MOSI and MISO). Clearly, this variant is restricted to a half duplex mode. It tends to be used for lower performance parts, such as small EEPROMs used only during system startup and certain sensors, and Microwire. As of this writing, few SPI master controllers support this mode; although it can often be easily bit-banged in software.

When someone says a part supports SPI or Microwire, you can normally assume that means the four-wire version.

However, when someone talks about a part supporting a 3-Wire serial bus you should always find out what they mean. They might mean standard four-wire SPI ... excluding the chipselect pin from that count, since most buses use chipselects but only three wires carry "real" signals. (Plus, sometimes with an unshared SPI bus segment the device's chipselect will be hard-wired as "always selected".) They might mean "real" 3-wire SPI. They might even mean an RS232 cable with just RXD, TXD, and shield/ground, or an application-specific signaling scheme.

References

ee also

*I²C, sometimes called "2-wire" bus
*1-Wire
*Microwire
*Computer bus
*Controller Area Network
*Serial communications
* Synchronous Serial Port (SSP)
*Peripheral
*Interface

External links

* [http://embedded.com/showArticle.jhtml?articleID=9900483 Introduction to Serial Peripheral Interface] article on embedded.com
* [http://www.epanorama.net/links/serialbus.html Serial buses information page]
* [http://www.mct.net/faq/spi.html SPI Introduction] with helpful diagrams
* [http://www.serialflash.com/ Serial Flash] Lots of good information on SPI part manufacturers and models.
* [http://ww1.microchip.com/downloads/en/DeviceDoc/spi.pdf SPI - PICmicro Serial Peripheral Interface] Microchip (company) tutorial on SPI.