- PWRficient
-
Power Architecture Historical POWER • POWER1 • POWER2 • POWER3 • POWER4 • POWER5 • PowerPC-AS • PPC6xx • PPC7xxx • PPC970 • Gekko • PA6T • Titan • AIM alliance
Current PowerPC • e200 • e300 • e500 • e600 • e5500 • QorIQ • POWER6 • POWER7 • PPC4xx • PPC7xx • PPC A2 • Cell • Xenon • Broadway
Future POWER8 • e6500
Related Links RISC • Blue Gene • Power.org • PAPR • PReP • CHRP • AltiVec • more...
PWRficient is the name of a series of microprocessors designed by P.A. Semi.
PWRficient processors comply with the 64-bit Power Architecture, and are designed for high performance and extreme power efficiency. The processors are highly modular and can be combined to multi-core system-on-a-chip designs, combining CPU, northbridge, and southbridge functionality on a single processor die.
The PA6T is the first processor core from P.A. Semi, and it is offered in two distinct lines of products, 16xxM dual core processors and 13xxM/E single core processors. The PA6T lines differ in their L2 cache size, their memory controllers, their communication functionality, and their cryptography offloading features. In the future P.A. Semi plans to offer parts with up to 16 cores.
The PA6T core is the first Power Architecture core to be designed from scratch outside the AIM alliance (i.e. not designed by IBM, Motorola/Freescale, or Apple Inc.) in ten years. Since Texas Instruments is one of the investors in P.A. Semi, it is suggested that their fabrication plants will be used to manufacture the PWRficient processors.[1]
PWRficient processors were initially shipped to select customers in February 2007 and were released for worldwide sale in Q4 2007.[2]
P.A. Semi was bought by Apple Inc. in April 2008,[3] and closed down development of PWRficient architecture processors. However, it will continue to manufacture, sell and support these components for the foreseeable future due to an agreement with the US Government, as the processors are used in some military applications.[4][5]
Contents
Implementation
PWRficient processors comprise three parts:
CPU
PA6T
- Superscalar, out-of-order 32-bit/64-bit Power Architecture processor core
- Adheres to the Power ISA v.2.04
- Little endian or big endian operation
- 64/64 KiB instruction and data L1 caches. 32 GB/s bandwidth.
- Six execution units including a double precision FPU and Altivec unit
- Hypervisor and virtualization support
- Maximum 7 W at 2 GHz
- 11 million transistors, 10 mm² large @ 65 nm.
Memory system
CONEXIUM
- scalable cross-bar interconnect
- 1–8 SMP cores
- 1–2 L2 caches, 512 KiB – 8 MiB large. 16 GB/s bandwidth.
- 1–4 1067 MHz DDR2 memory controllers. 16 GB/s bandwidth.
- 64 GB/s peak bandwidth
- MOESI coherency
I/O
ENVOI
- Centralized DMA engine, 32 GB/s bandwidth
- 16–64 SerDes lanes
- XAUI
- PCI Express
- SGMII
- Offload engine for cryptography, RAID, TCP
Notable users
- Curtiss-Wright will use the 1682M processor in its signal processing systems. [1][dead link]
- Mercury Computer Systems will use the 1682M processor in its signal and image processing systems. [2]
- NEC will use the 1682M processor in its storage array systems. [3]
- AmigaOne X1000 uses the 1682M processor as CPU.[4]
References
- ^ "PA Semi heads to 16 cores on back of $50m boost". The Register. http://www.theregister.co.uk/2006/05/17/pasemi_core_ti/. Retrieved 2006-10-17.
- ^ "Press release". P.A. Semi. http://pasemi.com/news/pr_2007_02_05b.html. Retrieved 2007-02-07.[dead link]
- ^ "Apple Buys Chip Designer". Forbes. 2008-04-23. http://www.forbes.com/2008/04/23/apple-buys-pasemi-tech-ebiz-cz_eb_0422apple.html. Retrieved 2011-07-05.
- ^ "Apple will please missile makers by backing PA Semi's chip". The Register. 2008-05-16. http://www.theregister.co.uk/2008/05/16/pasemi_apple_support/. Retrieved 2011-07-05.
- ^ "DoD may push back on Apple's P.A. Semi bid". EETimes. 2008-05-23. http://www.eetimes.com/electronics-news/4076837/DoD-may-push-back-on-Apple-s-P-A-Semi-bid. Retrieved 2011-07-05.
External links
Categories:- Power microprocessors
Wikimedia Foundation. 2010.
