Power Architecture

Power Architecture is a broad term to describe similar instruction sets for RISC microprocessors developed and manufactured by such companies as IBM, Freescale, AMCC, Tundra and P.A. Semi. The governing body is Power.org, comprising over 40 companies and organizations.

The term "Power Architecture" should not be confused with IBM's different generations of "POWER architectures" where the latter is a broad term including all products based on POWER, PowerPC and Cell architectures. Power Architecture is a family name describing processor architecture, software, toolchain, community and end-user appliances and not a strict term describing specific products or technologies.

Glossary

There can be misunderstanding of the meaning of the terms, POWER, PowerPC and Power Architecture. Here is a glossary with brief descriptions of each term, and links to articles with details.

History

Power Architecture began its life at IBM in the late 1980s when they wanted a high performance RISC architecture for their mid range workstations and servers. The result was the "POWER architecture" with its first implementation in 1990 in the RISC System/6000, later RS/6000, computers. This was the 10 chip RIOS-1 processor, later called POWER1. The RISC Single Chip (RSC) processor was developed from RIOS-1.

In 1992, Apple, Motorola and IBM formed the AIM alliance to develop a mass market version of the POWER processor. The result of this was the "PowerPC architecture", a modified version of the POWER architecture. The first implementation was the PowerPC 601 in 1993, based heavily on RSC, found its way into Apple's Power Mac computers as well as IBM RS/6000 systems.

IBM expanded their POWER architecture for their RS/6000 systems which resulted in the eight chip POWER2 processor 1993 and a single chip version called P2SC, "POWER2 Super Chip", 1996.

In the early 1990s IBM sought to replace the CISC based AS/400 minicomputers with a RISC architecture. This new architecture's development code name was called "Amazon" became referred to as the PowerPC-AS ("Advanced Series" or "Amazon Series") amongst engineers working on the project. PowerPC-AS was to be a multi-processor server platform based on RSC. As development continued at IBM Research labs to extend RSC to support a 64-processor inter-connect and add features specific to AS/400. RS/6000 developers joined in and added some POWER2 features and it all ended up in the 64-bit processors of the RS64 line in 1997, used in AS/400 and RS/6000 systems.

The AIM Alliance kept developing PowerPC in 1995 through 1997 and released the second generation PowerPC processors: The PowerPC 602 for set top boxes and game consoles, the PowerPC 603 geared towards the embedded market and portable computers, the PowerPC 604 towards workstations and PowerPC 620 was a 64-bit high performance processor for servers. The 602 and 620 never found widespread use but the 603, 604 and their successors became very popular in their respective fields. Motorola and IBM also made the "Book E"cite web |title=PowerPC Book E v.1.0 |publisher=IBM |date=2002-05-07 |url=http://www.ibm.com/chips/techlib/techlib.nsf/techdocs/852569B20050FF778525699600682CC7 |accessdate=2007-03-16 ] extension of PowerPC, used in embedded implementations: Motorola's PowerQUICC processors and IBM's PowerPC 400 family.

The last effort of the AIM Alliance was the third generation PowerPC 750 in 1997. Motorola and IBM went their separate ways in developing the PowerPC architecture after that. The "G3" processors found widespread use in both computer and embedded markets and IBM kept evolving the 750 family in the years to come but Motorola chose to focus on the embedded market with PowerPC SoC designs and what they called the fourth generation PowerPC, the PowerPC 7400 which incorporated Altivec, a SIMD unit. The "PowerPC G4" came 1999 and was used by Apple in workstations and laptops and by various companies in the telecom market.

In 1998 came POWER3 which unified the PowerPC and POWER2 architectures but was only used in IBM's RS/6000 servers.

2000 saw the last implementation of the PowerPC-AS architecture, the RS64-IV, used in AS/400 and RS/6000, now renamed eServer iSeries and eServer pSeries respectively. IBM also makes the Gekko processor for use in Nintendo's game console GameCube. It's based on the PowerPC 750CXe. IBM built the Rivina, experimental 64-bit PowerPC processor, which became the first microprocessor to surpass the 1 GHz mark.

In 2001 IBM introduced the POWER4 which unified and replaced the PowerPC-AS and POWER3 architectures.

In 2002 Apple desperately need a new high end PowerPC part and got IBM to make the 64-bit PowerPC 970. Apple described it as the fifth generation PowerPC or "G5". 970 is derived from POWER4 but lacks some server oriented features, but does have an AltiVec unit. The 970 and its descendants are used by Apple and IBM and some high end embedded applications.

Tundra buys the PowerPC 100 family microcontrollers from Motorola in 2003 which spun off its semiconductor division into a new company called Freescale Semiconductor in 2004.

Culturecom licenses PowerPC technology from IBM for their V-Dragon processor in 2003.

POWER5 from IBM, introduced in 2004, is an evolution from POWER4 and bumps the PowerPC specification to v.2.01,cite web |title=PowerPC Architecture Book |publisher=IBM |url=http://www.ibm.com/developerworks/eserver/articles/archguide.html |date=2003-12-10 |accessdate=2007-03-16] and again to v.2.02cite web |title=PowerPC Architecture Book, Version 2.02 |publisher=IBM |date=2005-02-24 |accessdate=2007-03-16 |url=http://www.ibm.com/developerworks/eserver/library/es-archguide-v2.html ] in 2005 with the POWER5+.

AMCC licenses IP and staff from IBM concerning the PowerPC 400 family in 2004.cite web |url=http://www.ibm.com/developerworks/library/pa-nljun04-amcc.html |title=AMCC and Power Architecture technology |publisher=IBM |accessdate=2008-02-24]

Motorola/Freescale renamed its PowerPC families to e200, e300, e500 and e600 and announces the future 64-bit e700.

is founded the same year, by IBM alongside 15 other companies, as an organization whose mission is to develop products revolving around the Power Architecture. Its purpose is to develop, enable and promote Power Architecture technology.cite web |url=http://www.power.org/news/pr/view?item_key=32f283c95428a73b1293053148a8c81e1a2361d1 |title=Power.org initiative to advance community of electronics innovation |publisher=Power.org |date=2004-12-02 |accessdate=2008-02-24]

2005 also saw the specifications of the Cell processor,cite web |title=Cell BE Architecture v.1.0 |publisher=IBM |date=2006-03-10 |accessdate=2007-03-16 |url=http://www.ibm.com/chips/techlib/techlib.nsf/techdocs/1AEEE1270EA2776387257060006E61BA ] jointly developed by IBM, Sony and Toshiba over a four year period. Its primary use is for Sony's PlayStation 3. Cell uses a single 64-bit Power Architecture core, and adds 8 independent SIMD cores called SPEs. IBM also reveals the Xenon-processor, a tri-core 64-bit processor for use in Microsoft's Xbox 360. With the 32-bit PowerPC based Broadway processor that Nintendo will use for its Wii console, IBM has put Power Architecture processors in all three of the major seventh generation game consoles.

P.A. Semi licenses Power Architecture technology from IBM for use in its upcoming PWRficient processors.

Freescale joins Power.org in 2006 and IBM makes the specifications of PowerPC 405 freely available to researchers and academia.

Rapport Inc announces Kilocore technology where 1024 8-bit processing elements are strapped to a 32-bit PowerPC core.

Power.org released the Power ISA version 2.03.cite web |title=Power ISA v.2.03 |publisher=Power.org |date=2006-08-29 |accessdate=2007-03-16 |url=http://www.power.org/resources/downloads/PowerISA_203.Public.pdf ] in September 2006. All previous PowerPC specifications will be compatible with the 64-bit Power ISA. This will among other things add VMX, virtualization and variable length encoding (VLE, 2-byte instructions added to previously 4-byte instructions) to the specification.

Power.org releases the Power Architecture Platform Reference, PAPR, in the fourth quarter of 2006. It provides the foundation for development of Power Architecture based computers using the Linux operating system.

In April 2007, Freescale and IPextreme opens up a licensing program for Freescale's PowerPC e200 core.cite web |url=http://www.power.org/news/pr/view?item_key=68b01acc02e0cc96b4f0e72103ee2182ea74c08b |title=Freescale opens licensing of Power Architecture e200 core family through IPextreme |publisher=Power.org |date=2007-04-02 |accessdate=2008-02-24]

In May 2007 IBM launches its POWER6 high end microprocessor at speeds up to 5.0 GHz, doubling the performance of the previous POWER5. The POWER6 adds AltiVec to the POWER series and an FPU supporting decimal arithmetic. The same day AMCC announced its Titan high end embedded processor, reaching 2 GHz while consuming very little power. It uses innovative logic design from Intrinsity and will be available in 2008.

The members of Power.org finalizezd the Power ISA v.2.04cite web |title=Power ISA Version 2.04 |publisher=Power.org |date=2007-06-12 |accessdate=2007-06-14 |url=http://www.power.org/resources/downloads/PowerISA_Public.pdf ] specification in June 2007. Improvements are mainly focused on server applications and virtualization.

At the Power Architecture Developer Conference in September 2007, drafts to Power ISA v.2.05 and ePAPR specification was shown, and a Linux based reference design based on PowerPC 970MP was revealed.cite web |title=Power.org Debuts Specification Advances and New Services At Power Architecture Developer Conference |publisher=Power.org |date=2007-09-24 |url=http://www.power.org/news/pr/view?item_key=20eea4d0ce638d7641d7d04d529d9369fee9e280 |accessdate=2007-09-24 ]

The Power ISA v.2.05 specification was released in December 2007.cite web |title=Power ISA Version 2.05 |publisher=Power.org |date=2007-10-23 |url=http://www.power.org/resources/reading/PowerISA_V2.05.pdf |accessdate=2007-12-18 ]

In April 2008, IBM rebrands their Power Architecture based hardware, System p and System i. They are now called "Power Systems". At the same time they rebranded the i5/OS operating system "IBM i".

On April 23, 2008, Apple acquired P.A. Semi for a reported $278 million. [cite web
title=Apple Buys Chip Designer
publisher=Forbes
url=http://www.forbes.com/technology/2008/04/23/apple-buys-pasemi-tech-ebiz-cz_eb_0422apple.html
accessdate=2008-04-23 ]

On May 25, 2008, IBM is the first to break the 1 Petaflops barrier with the Roadrunner supercomputer. [cite web
title=Fact Sheet & Background: Roadrunner Smashes the Petaflop Barrier
publisher=IBM
url=http://www-03.ibm.com/press/us/en/pressrelease/24405.wss
accessdate=2008-06-16 ] In June 2008, it entered the Top500 list of the fastest computers in the world on first place, replacing the BlueGene/L which had held that position since November 2004.

On June 16, 2008, Freescale announces QorIQ families P1, P2, P3, P4 and P5, the evolution of PowerQUICC, featuring the eight-core P4080. [cite web
title=Freescale QorIQ communications platforms signal a new way forward for embedded multicore technology
publisher=Freescale
url=http://media.freescale.com/phoenix.zhtml?c=196520&p=irol-newsArticle&ID=1165849
accessdate=2008-06-16 ]

In September 2008, the POWER7 based supercomputer Blue Waters gets green light. [http://www.networkworld.com/community/node/32152] For a cost of $208 million, with 200.000 processors, it'll bring multi petaflops performance in 2010-1011.

According to the TOP500-list (June 2008), the top three, six of the ten fastest supercomputers in the world and 22 of the top 50 are using IBM's technologies based on Power Architecture. Of the top ten, five use Power Architecture processors as computing elements and one use them as communications processors.

Licensing

The Power Architecture is open for licensing by third parties. Licencees can choose to license anything from a single predefined core, to a complete new family of Power Architecture products.

IBM licenses hard (predefined chip designs) and soft (synthesized design that can be used in different foundries) core implementations of both the 32-bit and 64-bit Power Architecture, either directly or through Power Design Center partners such as HCL Technologies or Synopsys. On a strategic basis, IBM also provide both microarchitecture and architecture licenses. A microarchitecture license enables licensees to implement a new pipeline for a core, but not to add or subtract instructions from the Power Instruction Set Architecture (ISA). Microarchitecture licenses cover both 64-bit and 32-bit, although individual licenses are available if necessary/desired.

IBM has announced plans to make the specifications of the PowerPC 405 core [http://www.power.org/news/articles/405download/ freely available] to the academic and research community.

In April 2007 Freescale and IPextreme opened up the PowerPC e200 cores for licensing to other manufacturers. Companies which have licenses developing their own processors based on the Power Architecture including Tundra, AMCC, HCL, Culturecom, P.A. Semi, Xilinx, Microsoft, Rapport, Sony, Honeywell, Toshiba and Cray.

Description

The Instruction Set architecture is divided into several "Categories" and every component is defined as a part of a category. And each category resides within a certain "Book". Processors implement a set of these categories. Different classes of processors are required to implement certain Categories, for example a server class processor use categories "Server", "Base", "Floating Point", "64-bit", etc. All processors implement the Base category.

It is a RISC load/store architecture. It has multiple set of registers:
* thirty-two 32-bit or 64-bit General Purpose Registers (GPRs) for integer operations.
* thirty-two 64-bit Floating Point Registers (FPRs) for floating point operations.
* thirty-two 128-bit Vector registers for vector operations.
* Eight 4-bit Condition register fields (CRs) for comparison and flow control.
* Special registers: Counter Register (CTR), Link Register (LR), Time Base (TBU, TBL), Alternate Time Base (ATBU, ATBL), Accumulator (ACC), Status registers (XER, FPSCR, VSCR, SPEFSCR).

Instructions have a 4-byte (32-bit) uniform length with the exception of the VLE (variable-length encoding) subset that provides for higher code density for low-end embedded applications. Most instructions are triadic, i.e. have two source operands and one destination. Single and double precision IEEE-754 compliant floating point operations are supported, including additional fused multiply add (FMA) and decimal floating-point instructions. There are provisions for SIMD operations on integer and floating point data on up to 16 elements in a single instruction.

Support for Harvard cache, i.e. split data and instruction caches, as well as support for unified caches. Memory operations are strictly load/store, but allow for out-of-order execution. Support for both big and little-endian addressing with separate categories for moded and per-page endianess. Support for both 32-bit and 64-bit addressing.

Different modes of operation: User, supervisor and hypervisor.

Categories

*Base – Most of Book I and Book II
*Server – Book III-S
*Embedded – Book III-E
*Misc – Floating Point, Vector, Signal Processing, Cache Locking, Decimal Floating-point, etc

Books

The Power Architecture specification is divided into multiple "books", five parts:
*Book I – "User Instruction Set Architecture" covers the base instruction set available to the application programmer. Memory reference, flow control, Integer, floating point, numeric acceleration, application-level programming. It includes chapters regarding auxiliary processing units like DSPs and the AltiVec extension.
*Book II – "Virtual Environment Architecture" defines the storage model available to the application programmer, including timing, synchronization, cache management, storage features, byte ordering.
*Book III – "Operating Environment Architecture" includes exceptions, interrupts, memory management, debug facilities and special control functions. It's divided into two parts.
**Book III-S – Defines the supervisor instructions used for general purpose/server implementations. It's mainly the contents of the Book III of the former PowerPC ISA.
**Book III-E – Defines the supervisor instructions used for embedded applications. It is derived from the former PowerPC Book E.
*Book VLE – "Variable Length Encoded Instruction Architecture" defines alternative instructions and definitions from Book I-III, intended for higher instruction density and very low end applications. They use 16-bit instructions and big endian byte ordering.

Specifications

Power ISA v.2.03

The specification for Power ISA v.2.03 is based on the former PowerPC ISA v.2.02 in POWER5+ and the Book E extension of the PowerPC specification. The Book I included five new chapters regarding auxiliary processing units like DSPs and the AltiVec extension.

Compliant cores
* e200, e500 and e700 from Freescale
* 405, 440, 460, 970, POWER5 and POWER6 from IBM,
* Cell PPE from IBM

Non-compliant cores
* MPC5xx, MPC8xx, e300 and G4/e600 from Freescale
* 6xx, 403 and 401 from IBM.
* POWER1, POWER2, POWER3, POWER4 and RS64 class processors from IBM.

Power ISA v.2.04

The specification for Power ISA v.2.04 was finalized in June 2007. It is based on Power ISA v.2.03 and includes changes primarily to the Book III-S part regarding virtualization, hypervisor functionality, logical partitioning and virtual page handling.

Compliant cores
* Cores that comply with the Power ISA v.2.03
* The PA6T core from P.A. Semi
* Titan from AMCC

Power ISA v.2.05

The specification for Power ISA v.2.05 was released in December 2007. It is based on Power ISA v.2.04 and includes changes primarily to Book I and Book III-S, including significant enhancements such as decimal arithmetic (Category: Decimal Floating-Point in Book I) and server hypervisor improvements.

Compliant cores
* Cores that comply with the Power ISA v.2.04
* POWER6

Power ISA v.2.06

Power ISA v.2.06 will include extensions for the POWER7 processor and e500-mc core. It will also include significant enhancement for the embedded specification regarding hypervisor and virtualisation on single and multi core implementations. It will be released the second half of 2008.

Implementations

Some examples.

Processors

* PowerPC processors from IBM, Freescale, Tundra, AMCC, PA Semi, Atmel, among others.
* PowerQUICC processors from Freescale
* POWER processors from IBM
* BlueGene/L processors for supercomputers by IBM
* The Cell processor from IBM, Sony and Toshiba
* Virtex FPGAs from Xilinx
* V-Dragon CPU from Culturecom
* Kilocore1025 from Rapport using Kilocore technology
* SeaStar and SeaStar2 communications processor in Cray XT3 and XT4 supercomputers

Systems

* System i and System p servers and BlueGene supercomputers from IBM
* PowerMac, pre-Intel iMac, iBook and PowerBook computers from Apple
* Bandai Pippin game system from Bandai (hardware and OS design by Apple)
* Pegasos/Open Desktop Workstation and EFIKA PowerPC based computers from Genesi
* TiVo series 1 DVR
* Cell BE and PowerPC based computers from Mercury
* GameCube and Wii game consoles from Nintendo
* Xbox 360 from Microsoft
* PlayStation 3 from Sony
* RAD6000 and RAD750, radiation hardened platforms by BAE Systems for use in space
* Routers from Cisco

* Printers, cars, aircraft, medical imaging, telecom equipment, spacecraft, RIPs, set top boxes, etc, from a multitude of companies.

Operating Systems

* Linux from various vendors
**Yellow Dog Linux from Terra Soft which is specialized for Power Architecture hardware
**MkLinuxThese operating systems are discontinued on Power Architecture] from Apple, based on Mach micro kernel
* NetBSD, OpenBSD, FreeBSD and OpenDarwin
* Classic Mac OSThese operating systems have been completely discontinued] and Mac OS X from Apple
* OS/2, AIX and i5/OS from IBM
* Solaris from Sun and OpenSolaris
* Windows NT from Microsoft
* Plan 9 from Bell Labs
* BeOS from Be Inc.
* OS-9 from RadiSys
* eCos open source RTOS
* INTEGRITY from Green Hills Software
* VxWorks from Wind River
* QNX
* LynxOS from LynuxWorks
* OSE from ENEA
* MorphOS from [http://morphos-team.net MorphOS Team]
* AmigaOS 4 from [http://www.hyperion-entertainment.biz Hyperion Entertainment]

References

External links

* [http://www.rootvg.net/column_risc.htm 27 years of IBM RISC]
* [http://www.ibm.com/developerworks/library/pa-powerppl POWER to the people – A history of chipmaking at IBM]
* [http://www.freescale.com/files/32bit/doc/ref_manual/PWRARCPRMRM.pdf Power Architecture Primer]
* [http://www.power.org/brand_center/home/PowerArch_PPC_v1.pdf PowerPC transition to Power Architecture Guidelines]
* [http://power.org Power.org]
* [http://www.ibm.com/power IBM's Power Architecture site]
* [http://www.freescale.com/powerpc Freescale's Power Architecture site]
* [http://www.amcc.com/powerpc/ AMCC's PowerPC site]
* [http://www.mc.com/cell/ Mercury's Cell BE site]
* [http://www.tundra.com/ Tundra's homepage]
* [http://www.pasemi.com P.A. Semi's homepage]
* [http://www.culturecom.com.hk/en/index.php?bx_vdragon Culturecom's V-Dragon site]
* [http://www.genesippc.com/ Genesi's homepage]
* [http://penguinppc.org/ Linux/PPC homepage]