PowerPC 600

The PowerPC 600 family was the first family of PowerPC processors built. They were designed at the Somerset facility in Austin, Texas, jointly funded and staffed by engineers from IBM and Motorola as a part of the AIM alliance. Somerset was opened in 1992 and its goal was to make the first PowerPC processor and then keep designing general purpose PowerPC processors for personal computers. The first incarnation became the PowerPC 601 in 1993, and the second generation soon followed with the PowerPC 603, PowerPC 604 and the 64-bit PowerPC 620.

The real family is the 601, 603, 604 and 620. All others are either derivative work or completely different processors, sharing the name only as prototypes.

Nuclear family

PowerPC 601

The PowerPC 601 was the first generation of microprocessors to support the basic 32-bit PowerPC instruction set. The design effort started in earnest in the summer of 1991 and the first prototype chips were available in the early fall 1992. The first 601 processors were introduced in an IBM RS/6000 workstation in October 1993 (alongside its more powerful multichip cousin IBM POWER2 line of processors) and the first Apple Power Macintoshes in April 1994. The 601 was the first advanced single-chip implementation of the POWER/PowerPC architecture designed on a crash schedule to establish PowerPC in the marketplace and cement the AIM alliance. In order to achieve an extremely aggressive schedule while including substantially new function (such as substantial performance enhancements, new instructions and importantly POWER/PowerPC's first symmetric multiprocessing (SMP) implementation) the design leveraged a number of key technologies and project management strategies. The 601 team leveraged much of the basic structure and portions of the IBM RISC Single Chip (RSC) processor, but also included support for the vast majority of the new PowerPC instructions not in the POWER instruction set. While nearly every portion of the RSC design was modified, and many design blocks were substantially modified or completely redesigned given the completely different unified I/O bus structure and SMP/memory coherency support. New PowerPC changes, leveraging the basic RSC structure was very beneficial to reducing the uncertainty in chip area/floorplanning and timing analysis/tuning. Worth noting is that the 601 not only implemented substantial new key functions such as SMP, but it also acted as a bridge between the POWER and the future PowerPC processors to assist IBM, Apple, and other system vendors and software groups in their transitions to PowerPC. From start of design to tape-out of the first 601 prototype was just 12 months in order to push hard to establish PowerPC on the market early.

60x bus

In order to help the effort to rapidly incorporate the 88110 bus architecture to the 601 for the benefit of the alliance and its customers, Motorola management provided not only the 88110 bus architecture specifications, but also a handful of 88110 bus-literate designers to help with the 60x bus logic implementation and verification. Given the Apple system design team was familiar with the I/O bus structure from Motorola's 88110 and this I/O bus implementation was well defined and documented, the 601 team adopted the bus technology to improve time to market. The bus was renamed the 60x bus once implemented on the 601. These Motorola (and a small number of Apple designers) joined over 120 IBM designers in creating the 601.
* [http://www-01.ibm.com/chips/techlib/techlib.nsf/techdocs/852569B20050FF7785256996007248B1/$file/60xbus.pdf The Bus Interface for 32-Bit Microprocessors – IBM.com]

Using the 88110 bus as the basis for the 60x bus helped schedules in a number of ways. It helped the Apple Power Macintosh team by reducing the amount of redesign of their support ASICs and it reduced the amount of time required for the processor designers and architects to propose, document, negotiate, and close a new bus interface (successfully avoiding the "Bus Wars" expected by the 601 management team if the 88110 bus or the previous RSC buses hadn't been adopted).Worthy to note is that accepting the 88110 bus for the benefit of Apple's efforts and the alliance was at the expense of the first IBM RS/6000 system design team's efforts who had their support ASICs already implemented around the RSC's totally different bus structure.This 60x bus later became a fairly long lived basic interface for the many variants of the 601, 603, 604, G3, G4 and Motorola/Freescale PowerQUICC processors.

Design

The chip was designed to suit a wide variety applications and had support for external L2 cache and symmetric multiprocessing. It had a four stage pipeline, 4 functional units, including a floating point unit, an integer unit, a branch unit and a sequencer unit (a little used heritage from the RSC). The processor also included a memory management unit.

First launched in IBM systems in the fall of 1993, it was manufactured by IBM as the PPC601 (but marketed by Motorola as MPC601), using a 0.6 µm aluminum based CMOS process, at speeds ranging from 50 to 80 MHz. The die was 121 mm² large, had 2.8 million transistors and included 32 kB unified L1 cache which was very much at the time. Thanks partly to the large cache it was considered a high performance processor in its segment, readily beating Intel's competitor Pentium. PowerPC 601 was used in the first Power Macintosh computers from Apple, and in a variety of RS/6000 workstations and SMP servers from IBM and GroupBull.

IBM was the sole manufacturer of the 601 & 601+ microprocessors in its Burlington, Vermont and East Fishkill, New York production facilities. The 601 used the IBM CMOS-4s process and the 601+ used the IBM CMOS-5x process. An extremely small number of these 601/601+ processors were relabeled with Motorola logos/part numbers and distributed through Motorola. These facts are somewhat obscured given there are various pictures of the "Motorola MPC601", particularly one specific case of masterful Motorola marketing where the 601 was named one of TIME Magazine's 1994 "Products of the Year" with a Motorola marking. The 601+ design was remapped from CMOS-4s to CMOS-5x by an IBM-only team. To avoid time-to-market delays from design tool changes and commonizing fab groundrules, both the 601 and 601+ were designed with IBM EDA tools on IBM systems and were fabricated in IBM-only facilities.

PowerPC 601v

An updated version, PowerPC 601v or PowerPC 601+, 74 mm² small using a 0.5 µm fabrication process, followed in 1994 with speeds 100-120 MHz.
* [http://www-03.ibm.com/systems/p/hardware/whitepapers/power/ppc_601.html PowerPC 601 Whitepaper]
* [http://arstechnica.com/articles/paedia/cpu/ppc-1.ars/2 Ars Technica article]

PowerPC 603

The PowerPC 603 was the first processor implementing the complete 32-bit PowerPC Architecture as specified. It was designed to be a low cost, low end processor for portable and embedded use. One of the main features was power saving functions (doze, nap and sleep mode) that could dramatically reduce power requirements, drawing only 2 mW in sleep mode. The 603 has a four stage pipeline and five execution units: integer unit, floating point unit, branch prediction unit, load/store unit and a system registry unit. It has separate 8 KB L1 caches for instructions and data and a 32/64 bit 60x memory bus, reaching up to 75 MHz. The 603 core doesn't support SMP in hardware.

The PowerPC 603 had 1.6 million transistors and was manufactured by IBM and Motorola on a 0.5 µm fabrication process. The die was 85 mm² large drawing 3W at 80 MHz. The 603 architecture is the direct ancestor to the PowerPC 750 architecture, marketed by Apple as the PowerPC "G3".

It was used in low end and portable Macintosh models but also found widespread use in different embedded appliances. The processor got a somewhat bad reputation in Apple's computers since the 68k emulation software didn't fit into the relatively small caches causing some degraded performance in older software. This poor performance made it unacceptable as a laptop CPU and was not used in such, delaying the Apple PowerBook 5300 and PowerBook Duo 2300 introduction.
* [http://www-03.ibm.com/servers/eserver/pseries/hardware/whitepapers/power/ppc_603.html IBM white paper about PowerPC 603]

PowerPC 603e / 603ev

The performance issues of the 603 were addressed in the PowerPC 603e. The L1 cache was enlarged and enhanced to 16 kB four-way set-associative data and instruction caches. The clock speed of the processors was doubled too, reaching 200 MHz. Shrinking the fabrication process to 0.35 µm allowed for speeds of up to 300 MHz. This part is sometimes called PowerPC 603ev. The 603e and 603ev have 2.6 million transistors each and are 98 mm² and 78 mm² large respectively. The 603ev draws a maximum of 6 W at 300 MHz.

The PowerPC 603e was the first mainstream desktop processor to reach 300 MHz. The 603e was also used in accelerator cards from Phase5 for the Amiga line of computers, with CPUs ranging in speeds from 160 to 240 MHz. The PowerPC 603e is still sold today by IBM and Freescale, and others like Atmel and Honeywell who makes the radiation hardened variant RHPPC. The PowerPC 603e was also the heart of the BeBox from Be Inc. The BeBox is notable since it is a multiprocessing system, something the 603 wasn't designed for. IBM also used PowerPC 603e processors in the ThinkPad 800 series laptop computers. The 603e processors also power all 66 Iridium satellites. The satellites each contain seven Motorola/Freescale PowerPC 603E processors running at roughly 200 MHz each.
* [http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC603E Freescale's 603e page]
* [http://www-306.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_603e_Microprocessor IBM's 603e page]

G2

The PowerPC 603e core, renamed G2 by Freescale, is the basis for many embedded PowerQUICC II processors, and as such it keeps on being developed. Freescale's PowerQUICC II SoC processors bear the designation MPC82xx, and come in a variety of configurations reaching 450 MHz.

e300

Freescale has enhanced the 603e core, calling it e300, in the PowerQUICC II Pro embedded processors. Larger 32/32 KB L1 caches and other performance enhancing measures were added. Freescale's PowerQUICC II Pro SoC processors bear the designation MPC83xx, and come in a variety of configurations reaching speeds up to 667 MHz. The e300 is also the core of the MPC5200B SoC processor that is used in the small EFIKA computer.

PowerPC 604

The PowerPC 604 was introduced in 1994 alongside the 603 and was designed as a high performance chip for workstations and entry level servers and as such had support for symmetric multiprocessing in hardware. The 604 was used extensively in Apple's high end systems and was also used in Macintosh clones, IBM's low end RS/6000 servers and workstations, accelerator boards to Amigas and as an embedded CPU for telecom applications.

The 604 is a superscalar processor capable of issuing four instructions simultaneously. The 604 has a six stage pipeline and six execution units that can work in parallel, finishing up to six instructions every cycle. Two simple and one complex integer units, one floating point unit, one branch processing unit managing out-of-order execution and one load/store unit. It has separate 16 KB data and instruction L1 caches and a 32/64 bit 60x memory bus, reaching up to 50 MHz.

The PowerPC 604 contains 3.6 million transistors and was fabricated by IBM and Motorola with a 0.5 µm CMOS process. The die was 196 mm² large and drew 14 to 17W at 133 MHz. It operated at speeds between 100 and 180 MHz.
* [http://arstechnica.com/articles/paedia/cpu/ppc-1.ars/6 PowerPC on Apple: An Architectural History, Part I/PowerPC 604]

PowerPC 604e

The PowerPC 604e was introduced in 1996 and added a condition register unit and separate 32 KB data and instruction L1 caches among other changes to its memory subsystem and branch prediction unit, resulting in a 25% performance increase compared to its predecessor. It had 5.1 million transistors and was manufactured by IBM and Motorola on a 0.35 µm fabrication process. The die was 148 mm² or 96 mm² large, manufactured by Motorola and IBM respectively, drawing 16-18W at 233 MHz. It operated at speeds between 166 and 233 MHz and supported a memory bus up to 66 MHz.
* [http://www-3.ibm.com/chips/techlib/techlib.nsf/products/PowerPC_604e_Microprocessor IBM's PowerPC 604e page]
* [http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC604E-ARCHIVED&nodeId=01z3Tw9059r4bp# Freescale's PowerPC 604e page]

PowerPC 604ev "Mach5"

The PowerPC 604ev, 604r or "Mach 5" was introduced in 1997 and was essentially a 604e fabricated by IBM and Motorola with a newer process, reaching higher speeds with a lower energy consumption. The die was 47 mm² small manufactured on a 0.25 µm process drawing 6W at 250 MHz. It operated at speeds between 250 and 400 MHz and supported a memory bus up to 100 MHz.

While Apple dropped the 604ev in 1998, in favor for the PowerPC 750, IBM kept using it in entry-level models of its RS/6000 computers for several years.

PowerPC 620

The PowerPC 620 was the first 64-bit processor implementing the entire PowerPC Architecture. It was a second generation PowerPC alongside the 603 and 604, but geared towards the high end workstation and server market. It was powerful on paper and was initially supposed to be launched alongside its brethren but it was delayed until 1997. When it did arrive, the performance was comparably poor and the considerably cheaper 604e beat it. The 620 was therefore never produced in large quantities and found very little use. The sole user of PowerPC 620 was Groupe Bull in its Escala UNIX machines, but they didn't deliver any large numbers. IBM, which intended to use it in workstations and servers, decided to wait for the even more powerful RS64 and POWER3 64-bit processors instead.

The 620 was similar to the 604. It has a five stage pipeline, same support for symmetric multiprocessing and the same number of execution units; a load/store unit, a branch unit, an FPU, and three integer units. With a larger 32/32 KB L1 cache, access to up to 128 MB large L2 caches, and more powerful branch and load/store units that had more buffers, the 620 was very powerful. The branch prediction table was also larger and could dispatch more instructions so that the processor can handle out of order execution more efficiently than the 604. The floating point unit was also enhanced compared to the 604. With a faster fetch cycle and support for several key instruction in hardware (like sqrt) made it, combined with faster and wider data buses, more efficient than the FPU in the 604.

The system bus was a wider and faster 128 bit memory bus called the "6XX bus" and was also used in POWER3, RS64 and 601 and 604 based RS/6000 systems (with a bridge chip). The bus later evolved into the "GX bus" of the POWER4, and later GX+ and GX++ in POWER5 and POWER6 respectively.

The 620 was produced by Motorola in a 0.5 µm process, it had 6.9 million transistors, and the die was 311 mm² large. Speeds at 120-150 MHz, drawing 30 W at 133 MHz. A later model was built using a 0.35 µm, reaching 200 MHz.
* [http://www.byte.com/art/9411/sec8/art5.htm Article in BYTE]
* [http://www.feb-patrimoine.com/Histoire/temoignages/histoire_unix_chez_bull_12_2004.pdf Contribution to the history of Unix at Bull] (Interesting reading concerning the use of PowerPC 620 at Bull. In French)

Extended family

PowerPC 602

The PowerPC 602 was a stripped down version of PowerPC 603, specially made for game consoles by Motorola and IBM in 1995. It has reduced L1 caches (4k instruction and 4k data), a singe-precision floating point unit and a back scaled branch prediction unit. It was offered at speeds ranging from 50 to 80 MHz, and drew 1.2 W at 66 MHz. It consisted of 1 million transistors and it was 50 mm² large manufactured at a 0.5 µm process.

3DO developed the M2 game console with two PowerPC 602, but it was never marketed.
* [http://www.cpushack.net/CIC/embed/announce/IBMPowerPC602.html Article at the CPUShack]

PowerPC 603Q

In 1996 the fabless semiconductor company Quantum Effect Devices (QED) made a PowerPC 603 compatible processor named "PowerPC 603Q" which didn't have anything, but the name, in common with any other 603. It was a from ground up implementation of the 32 bit PowerPC specification targeted at the high end embedded market. As such it was small, simple, energy efficient, but powerful; equaling the more expensive 603e while drawing less power. It had an in order, 5 stage pipeline with a single integer unit, a double precision floating point unit and separate 16 kB instruction and 8 kB data caches. It was 69 mm² small using a 0.5 µm fabrication process and drew just 1.2 W at 120 MHz.

603Q was designed for Motorola, but they withdrew from the contract before 603Q went into full production and QED could not continue to market the processor since they lacked a PowerPC license of their own.
* [http://cpushack.net/CIC/announce/1996/QEDPowerPCq.html Article at the CPUShack]

PowerPC 613

"PowerPC 613" seems to be a name Motorola had given a third generation PowerPC. It supposedly was renamed "PowerPC 750" in response to Exponential's x704 processor that was designed to outgun the 604 by a wide margin. There are hardly any sources confirming any of this though and it might be pure speculation, or a reference to a completely different processor.

PowerPC 614

Similar to PowerPC 613, the "PowerPC 614" might have been a name given by Motorola to a third generation PowerPC, and later renamed by the same reason as 613. It's been suggested that the part was renamed "PowerPC 7400", and Motorola even bumped it to the fourth generation PowerPC even though the architectural differences between "G3" and "G4" was small. There are hardly any sources confirming any of this though and it might be pure speculation, or a reference to a completely different processor.

PowerPC 615

The "PowerPC 615" is a little known PowerPC processor announced by IBM in 1994. Its main feature was to incorporate an x86 core on die, thus making the processor able to natively process both PowerPC and x86 instructions. An operating system running on PowerPC 615 could either chose to execute 32 bit or 64 bit PowerPC instructions, 32 bit x86 instructions or a mix of three. Mixing instructions would involve a context switch in the CPU with a small overhead. Minix and a special developer version of OS/2 could run.

It was 330 mm² large and manufactured by IBM on a 0.35 µm process. It was pin compatible with Intel's Pentium processors and comparable in speed. The processor was only produced in prototype examples and the program was killed in part by the fact that Microsoft would probably never give support for the processor. Engineers working on the PowerPC 615 would later find their way to Transmeta working on their Crusoe processor.
* [http://www.theregister.co.uk/1998/10/01/microsoft_killed_the_powerpc/ Article in The Register]
* [http://www.byte.com/art/9511/sec7/art15.htm Article in BYTE]

PowerPC 625

"PowerPC 625" was the early name for the Apache series 64-bit PowerPC processors, designed by IBM based on the "Amazon" PowerPC-AS instruction set. They were later renamed "RS64". The designation "PowerPC 625" was never used for the final processors.

PowerPC 630

"PowerPC 630" was the early name for the high end 64-bit PowerPC processor, designed by IBM to unify the POWER and PowerPC instruction sets. It was later renamed "POWER3", probably to separate it from the more consumer oriented "PowerPC" processors used by Apple.

PowerPC 641

"PowerPC 641", codename "Habanero", is a defunct PowerPC project by IBM in the 1994-96 timeframe. It has been suggested that was the third generation PowerPC based on the 604 processor. [http://zmoore.net/CRM%20Resume%20070904.pdf] [http://www.mackido.com/Hardware/G3.html]

See also

* PowerPC
** PowerPC G3
** PowerPC G4
** PowerPC 970
* IBM POWER
* Power Architecture