PowerPC e500

The PowerPC e500 is a 32-bit Power Architecture based microprocessor core from Freescale. The core is compatible with the older PowerPC Book E specification as well as the current Power ISA v.2.03. It has a dual issue, seven stage pipeline with FPUs, 32/32 KiB data and instruction L1 caches and 256, 512 or 1024 KiB L2 frontside cache. Speeds range from 533 MHz up to 1.5 GHz, and the core is designed to be highly configurable and meet the specific needs of embedded applications with features like multi core operation and interface for auxiliary application processing units (APU).

e500 powers the high-performance PowerQUICC III system on a chip (SoC) network processors and they all share a common naming scheme, MPC85xx. Freescale's new QorIQ is the evolutionary step from PowerQUICC III and will also be based on e500 cores.

There are three versions of the e500 core, namely the original e500v1, the e500v2 that is in use in most of the .

e500v2

Key improvements in the e500v2 over the e500v1 include:
* increase from 32-bit (4GiB) to 36-bit (64GiB) physical address space (this change means that e500v2-based devices often use a more advanced BSP than e500v1-based devices, as various peripheral units have moved to physical addresses > 2^32).
* addition of 1GiB and 4GiB variable-page sizes
* addition of double precision floating point support
* doubling in size and associativity of the MMU's second-level 4K-page array (from 256-entry 2-way to 512-entry 4-way)
* increase from 3 to 5 maximum outstanding data cache misses
* addition of the Alternate Time Base for cycle-granularity timestamps

e500mc

Freescale introduced the e500mc in the QorIQ family of chips in June 2008. The e500mc has the following features:
* PowerISA v.2.06, which includes hypervisor and virtualisation functionality for embedded platforms.
* Support anything from 2 to more than 32 cores (not necessarily the same type of cores) on a a single chip.
* Supports the CoreNet communications fabric for connecting cores and datapath accelerators.
* e500mc cores have private L2 caches but typically share other facilities like L3 caches, memory controllers, application specific acceleration cores, I/O and such.

Note on spelling: Freescale calls the new e500 the "e500mc" [ [http://www.freescale.com/files/32bit/doc/white_paper/EMBEDDED_HYPERVISOR.pdf?fsrch=1 For example, this white paper talks about e500mc] , see also [http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=P4080&fastpreview=1&fpsp=1&tab=Documentation_Tab QorIQ P4080 product summary] ] . Also, previous versions of this wikipedia article called the on-chip interconnect "FlexNet", rather than "CoreNet". FlexNet is a software protection product from Macrovision.

Applications

PowerQUICC

All PowerQUICC 85xx devices are based on e500v1 or e500v2 cores, most of them on the e500v2.

QorIQ

In June 2008 Freescale announced the QorIQ brand, microprocessors based on e500 cores. The QorIQ P1 and P2 families are using e500v2 while the P3, P4 and P5 families are using the e500mc cores and CoreNet communications fabric.

See also

* Power Architecture
* PowerQUICC
* QorIQ
* PowerPC e200

References

* [http://www.freescale.com/powerquicc Freescale's PowerQUICC page]
* [http://www.phxmicro.com/Online/E500CORERM.pdf Freescale's PowerPC e500 Core Family Reference Manual]