POWER5

POWER5 is a microprocessor developed by IBM. It is an improved variant of the highly successful POWER4. The principal changes are support for Simultaneous multithreading (SMT) and an on-die memory controller. Each CPU supports 2 threads; since it is a multicore chip, with 2 physical CPUs, each chip supports 4 logical threads. The POWER5 can be packaged in a DCM (dual chip module), with one dual core chip per module, or an Multi-Chip Module (MCM) with 4 dual core chips per module. POWER5+ (presented on 3Q 2005) packages in QCM, 2 dual core chips.

Several POWER5 processors in high end systems can be coupled together to act as a single vector processor by a technology called ViVA, Virtual Vector Architecture.

IBM uses the POWER5 processors in their System p and System i server families as well as controllers in their high end Infoprint printers and the DS8000 storage server. Bull also uses the POWER5 in their Escala servers. Several Hitachi SR11000 computers with up to 128 POWER5+ CPUs can be found amongst the Top500 supercomputers (2007).

QCM support for IBM System p5 servers [http://www.redbooks.ibm.com/redpapers/pdfs/redp4150.pdf] :
* IBM System p5 510Q
* IBM System p5 520Q
* IBM System p5 550Q
* IBM System p5 560Q

See also

*IBM System p
*IBM POWER
*Power Architecture
*PowerPC
*POWER6

External links

* [http://www.realworldtech.com/page.cfm?ArticleID=RWT100404214638 Sizing up the Super Heavyweights] , a comparison and analysis of the POWER5 and Montecito, that explains the major changes between the POWER4 to the POWER5, along with performance estimates

* [http://www.research.ibm.com/journal/rd/494/sinharoy.html IBM Journal of Research and Development: POWER5 System Microarchitecture] , a paper which describes the major differences between POWER5 and POWER4+ including specific details of how SMT was added and various other system-level improvements