Titan (microprocessor)

Titan is a family of 32-bit Power Architecture based microprocessors designed by Applied Micro Circuits Corporation (AMCC).

It is designed to be the foundation of embedded processors and system-on-a-chip (SoC) solutions. While being high performance reaching speeds up to 2 GHz, it remains extremely power efficient, drawing just 2.5 W per core. Where there usually is a trade off between performance and power, AMCC used the "Fast14" technology from Intrinsity to build an extremely efficient microprocessor design leveraging high performance combined with low power and comparably cheap bulk 90 nm CMOS manufacturing. By using NMOS transistors and no latches, the design results in a chip with fewer transistors than traditional design, thus reducing cost. The design allows for dual core SoC implementations consuming less than 15 W.

The Titan has a new superscalar, out of order 8-9 stage core with a novel three stage cache design. Small 4/4 KiB instruction and data caches at "level 0" sits before the traditional 32/32 KiB L1 caches and a 1 MB L2 cache that will be shared between all cores (supporting up to four). The Titan is compliant with the Power ISA v.2.04.

The first implementaions of the Titan design, slated for release in 2008, will be two dual core parts aimed at telecom and control plane applications. They will be built using TSMCs 90 nm bulk CMOS fabrication. There are plans for single core and quad core versions in the future.

See also

* AMCC
* Power Architecture

External links

* [http://investor.amcc.com/releasedetail.cfm?ReleaseID=244596 AMCC's pressrelease]
* [http://www.power.org/devcon/07/Session_Downloads/PADC07_Chang_AMCC_Titan_V0_2.pdf AMCC Next Generation Power Architecture Processor - Titan – Power.org]

* [http://www.eetimes.com/rss/showArticle.jhtml?articleID=199501275&pgno=1 AMCC drives to high end of embedded PowerPC market – EETimes]
* [http://www.marketwire.com/mw/release_html_b1?release_id=255717 Intrinsity Nets 2 GHz, 4000 DMIPS PowerPC FastCore - Market Wire]