IBM RS64

The IBM RS64 family of processors is used in the late 1990s for IBM's RS/6000 and AS/400 server product lines.

The family is using an instruction set called "Amazon", or "PowerPC-AS". It contains a subset of the PowerPC instruction set, with the addition of special features not in the PowerPC specification, especially derived from POWER2 and AS/400, and has been 64-bit from the start. The processors in this family are optimized for commercial workloads (integer performance, large caches, branches) and do not feature the strong floating point performance of the processors in the IBM POWER family, its sibling.

The RS64 family was phased out soon after the introduction of the POWER4.

Cobra and Muskie

In 1995 IBM released the Cobra, or A10 in AS/400 system. It was a single-chip processor running at 50-77 MHz. It was manufactured on a 0.6 µm aluminium process.

In 1996 IBM released the high-end, 4-way SMP, multi-chip version called Muskie, A25 or A30 in AS/400. It ran at 125-154 MHz. It was manufactured on a BiCMOS fabrication process.

These processors was only used in AS/400 machines.

RS64

The RS64 or Apache was introduced in 1997. It was developed from "Cobra" and "Muskie" but included a more complete PowerPC ISA and was therefore set to be used in RS/6000 machines as well as in AS/400 systems. It featured 128 KB total on-die L1 cache, 4 MB full speed off-chip L2 on a 128 bit bus, and a clock of 125 MHz. It scaled to a 12 processor SMP configuration in IBM's machines.

RS64 was called "A35" in AS/400 and was one time referred to as "PowerPC 625" [http://www.cbronline.com/article_cg.asp?guid=F5C9A2A8-3F4E-4CE1-ADC1-499264C9066C] , between the defunct PowerPC 620 and PowerPC 630 which was later renamed POWER3.

It was manufactured with a BiCMOS fabrication process.

RS64-II

The RS64-II or Northstar was introduced at 262 MHz in 1998 with 8 MB of full speed L2 on a 256 bit 6XX bus (also used in PowerPC 620 and POWER3). Processor boards containing 4 RS64-II's could be swapped into machines designed for similar 4-way RS64 boards, avoiding a "fork lift upgrade". The RS64-II contained 12.5 million transistors, was 162 mm² large and drew 27 Watts maximum power. Manufacturing changed to a 0.35 μm CMOS fabrication.

RS64-II was called "A50" in AS/400 systems.

RS64-III

The RS64-III or Pulsar was introduced in 1999 at 450 MHz. Key changes included larger 128 KiB L1 instruction and data caches, improved branch prediction accuracy and reduced branch misprediction penalties of zero or one cycle. The RS64-III has a five stage pipeline and a 256 bit wide L2 cache bus, which provided the processor with 14.4 GB/s of bandwidth from the 8 MiB L2 cache, implemented with 225 MHz DDR SRAMs.

The RS64-III has 34 million transistors, a die size of 140 mm², and is manufactured on the 0.22 μm CMOS 7S process with six levels of copper interconnect.

In 2000, IBM launched a refined version called IStar manufactured with a SOI fabrication process with copper interconnects, which increased the processor's clock frequency to 600 MHz. This was the first processor implemented in this process. Architecturally however, the IStar was identical to Pulsar.

RS64-IV

The RS64-IV or Sstar was introduced in 2000 at 600 MHz, later increased to 750 MHz. Up to 16 MB DDR L2 was supported in the same manner as the RS64-III (19.2 GB/s bandwidth). It was the first mass-market processor to implement multithreading. Essentially, each chip stores state information for 2 threads at any given time and appears to be two processors to the OS. One logical processor runs what is called the foreground thread. When this thread encounters a high latency event (L2 cache miss, etc) the background thread is switched to, on the second logical processor from the OS's point of view. In the event of a "less long" latency event (L1 miss, etc), thread switching will only occur if the background thread is ready to execute. If the background thread is also waiting for a miss, thread switching will not occur. IBM calls this scheme "coarse grained multithreading". It is not exactly the same thing as simultaneous multithreading as found on later Pentium 4 processors. An IBM paper notes that the coarse grained scheme is a better fit for an in-order architecture like RS64.

The RS64-IV had 44 milion transistors and was 128 mm² large manufactured on a 0.18 μm process. Unlike POWER, energy consumption remained low, at under 15 watts per core.

For a time, while the POWER line stagnated at half the clock speed of its competitors, the RS64 family was at the top of the IBM large SMP UNIX server line. The integer / commercial workload performance of the RS-64 IV was similar to the Sun Microsystems processors with which it competed, though its floating point power was not comparable to the contemporary POWER3-II, which remained reasonably competitive throughout its lifecycle.

External links

* [http://www.research.ibm.com/journal/rd/446/borkenhagen.html IBM paper on RS64-IV]
* [http://www.rootvg.net/column_risc.htm 27 years of IBM RISC]
* [http://www.the400squadron.com/amug/200406/NotPowerPC.htm When Is PowerPC Not PowerPC?] - History of the POWER Architecture by Frank Soltis
* [http://www-106.ibm.com/developerworks/linux/library/l-powhist/ "POWER to the people"]
* [http://www.csee.umbc.edu/help/architecture/ppcnstar.pdf 4th Generation 64-bit PowerPC-Compatible Commercial Processor Design]