A Serializer/Deserializer (SerDes pronounced sir-deez) is a pair of functional blocks commonly used in high speed communications to compensate for limited input/output. These blocks convert data between serial data and parallel interfaces in each direction. The term "SerDes" generically refers to interfaces used in various technologies and applications.


Generic function


The basic SerDes function is made up of two functional blocks: the Parallel In Serial Out (PISO) block (aka Parallel-to-Serial converter) and the Serial In Parallel Out (SIPO) block (aka Serial-to-Parallel converter). There are 4 different SerDes architectures: (1) Parallel clock SerDes, (2) Embedded clock SerDes, (3) 8b/10b SerDes, (4) Bit interleaved SerDes.

The PISO (Parallel Input, Serial Output) block typically has a parallel clock input, a set of data input lines, and input data latches. It may use an internal or external Phase-locked loop (PLL) to multiply the incoming parallel clock up to the serial frequency. The simplest form of the PISO has a single shift register that receives the parallel data once per parallel clock, and shifts it out at the higher serial clock rate. Implementations may also have a double-buffered register.

The SIPO (Serial Input, Parallel Output) block typically has a receive clock output, a set of data output lines, and output data latches. The receive clock may have been recovered from the data by the serial clock recovery technique. However, SerDes which do not transmit a clock use reference clock to lock the PLL to the correct Tx frequency, avoiding low harmonic frequencies present in the data stream. The SIPO block then divides the incoming clock down to the parallel rate. Implementations typically have two registers connected as a double buffer. One register is used to clock in the serial stream, and the other is used to hold the data for the slower, parallel side.

Some types of SerDes include encoding/decoding blocks. The purpose of this encoding/decoding is typically to place at least statistical bounds on the rate of signal transitions to allow for easier clock recovery in the receiver, to provide framing, and to provide DC balance.

Parallel clock SerDes

Parallel clock SerDes is normally used to serialize a parallel bus input along with data address & control signals. The serialized stream is sent along with a reference clock. The clock jitter tolerance at the serializer is 5-10 ps rms.

Embedded clock SerDes

An embedded clock SerDes serializes data and clock into a single stream. One cycle of clock signal is transmitted first, followed by the data bit stream; this creates a periodic rising edge at the start of the data bit stream. As the clock is explicitly embedded and can be recovered from the bit stream, the serializer (transmitter) clock jitter tolerance is relaxed to 80-120 ps rms, while the reference clock disparity at the deserializer can be +/-50000 ppm.

8b/10b SerDes

8b/10b SerDes maps each data byte to a 10bit code before serializing the data. The deserializer uses the reference clock to monitor the recovered clock from the bit stream. As the clock information is synthesized into the data bit stream, rather than explicitly embedding it, the serializer (transmitter) clock jitter tolerance is to 5-10 ps rms; and the reference clock disparity at the deserializer is +/-100ppm.

A common coding scheme used with SerDes is 8B/10B encoding. This supports DC-balance, provides framing, and guarantees frequent transitions. The guaranteed transitions allow a receiver to extract the embedded clock. The control codes allow framing, typically on the start of a packet. The typical 8B/10B SerDes parallel side interfaces have one clock line, one control line and 8 data lines.

Such serializer-plus-8B/10B encoder, and deserializer-plus-decoder blocks are defined in the Gigabit Ethernet specification.

Another common coding scheme used with SerDes is 64B/66B encoding. This scheme statistically delivers DC-balance and transitions through the use of a scrambler. Framing is delivered through the deterministic transitions of the added framing bits.

Such serializer-plus-64B/66B encoder and deserializer-plus-decoder blocks are defined in the 10 Gigabit Ethernet specification. The transmit side comprises a 64B/66B encoder, a scrambler, and a gearbox that converts the 66B signal to a 16 bit interface. A further serializer then converts this 16 bit interface into a fully serial signal.

Bit interleaved SerDes

Bit interleaved SerDes multiplexes several slower serial data streams into faster serial streams, and the receiver demultiplexes the faster bit streams back to slower streams.

See also


External links

Wikimedia Foundation. 2010.

Нужно решить контрольную?

Look at other dictionaries:

  • SerDes Framer Interface — is abbreviated as SFI. Some commonly used SFI variants include:* SFI 4: SerDes Framer Interface Level 4 * SFI 5: SerDes Framer Interface Level 5ee also*Optical Internetworking Forum …   Wikipedia

  • SerDes Framer Interface Level 5 — or SFI 5 is a standardized Electrical Interface standard by the OIF for connecting a Sonet Framer component to an optical SerDes for OC 768 (40 Gbit/s). [cite book|first=Panos C|last=Lekkas|title=Network Processors:Architecture, Protocols, and… …   Wikipedia

  • SERDES — Serialization/ De serialization (Academic & Science » Electronics) …   Abbreviations dictionary

  • QorIQ — is Freescale s brand of future 32 bit Power Architecture based communications microcontrollers. It is the evolutionary step from the PowerQUICC platform and will be built around one or more Power Architecture e500mc cores and come in five… …   Wikipedia

  • Optical Internetworking Forum — The Optical Internetworking Forum (OIF) is a non profit, member driven organization founded in 1998. It promotes the development and deployment of interoperable networking solutions and services through the creation of Implementation Agreements… …   Wikipedia

  • OBSAI — OBSAI, which stands for Open Base Station Architecture Initiative , is an initiative created by Hyundai, LGE, Nokia, Samsung and ZTE in September 2002 with the aim of creating an open market for cellular base stations. The idea behind this… …   Wikipedia

  • SFI-4 — or SerDes Framer Interface Level 4 is a standardized Electrical Interface by the OIF for connecting a Sonet Framer component to an optical SerDes for OC 192 interfaces (10 Gbit/s). [Lekkas, Network Processors:Architecture, Protocols, and… …   Wikipedia

  • Super I/O — (англ. Super Input/output, дословно: супер <контроллер> ввода/вывода)  название класса сопроцессоров, которые начали использоваться после 1980 х годов на материнских платах IBM PC совместимых компьютеров путём сочетания функций… …   Википедия

  • MoSys — Not to be confused with MOSIS. MoSys, Inc. Type Public (NASDAQ: MOSY) Industry Fabless semiconductor company (IC) Headquarters Santa Clara, California United States …   Wikipedia

  • Delay-locked loop — Une Delay locked loop (DLL) est un dispositif électronique permettant de changer la phase d un signal d horloge. Son fonctionnement est similaire à celui d une Phase Locked Loop, la différence principale étant l absence de VCO dans la DLL. Une… …   Wikipédia en Français

Share the article and excerpts

Direct link
Do a right-click on the link above
and select “Copy Link”