Platform Controller Hub

The Platform Controller Hub (PCH) is a family of Intel microchips employed in redesigned Intel Hub Architecture chipsets. PCH-based chipsets are designed to address the eventual problem of a bottleneck between the processor and the motherboard. As processing speeds/cores keep increasing, the bandwidth connection between the CPU and the motherboard would reach full capacity and a bottleneck would occur. The speed would be limited by the front-side bus (FSB). As a solution, the new PCH-oriented platform architecture transferred several functions, connections, and controllers belonging to the traditional northbridge and southbridge chipsets and rearranged them between a new central hub called the PCH and the CPU. In summary, the PCH takes over most of the traditional roles of the southbridge and the few remaining roles traditionally in the northbridge that have not been incorporated into the CPU package.

Before the Platform Controller Hub, a motherboard would have a two piece chipset consisting of a northbridge chip and a southbridge chip. The northbridge, later called a Memory Controller Hub (MCH), would have the highest bandwidth functions. The CPU, memory, and AGP or PCI Express graphics slot, if present, would connect to it directly. The northbridge's connection with the CPU, called the Front-Side Bus (FSB), and connection to RAM, called the back-side bus, were each described by data transfer speeds. The southbridge chip, later called an I/O Controller Hub (ICH), would connect the northbridge to all other lower bandwidth peripherals such as hard drives, CD and floppy drives, Ethernet, keyboard/mouse, PCI cards, system clock, and PCI graphics cards. As CPUs gained more speed and more cores, the connection between the CPU and the northbridge chip would soon be unable to keep up with the CPU thereby slowing the system down. So the connection needed a bigger pipeline.

Several changes have taken place with the evolution to PCH-based chipsets in comparison to the earlier MCH plus ICH based chipsets. The primary change is that the northbridge has been eliminated completely and most of its functions, e.g., the integrated memory controller (IMC) and integrated graphics device (IGD), are now incorporated into the CPU package (often on the same die). Secondly, the PCH now becomes the southbridge and incorporates all of its functions as well as a few of the remaining northbridge functions not subsumed by the CPU (e.g., clocking). Before, the memory RAM and the graphics card would communicate with the northbridge chipset which in turn would communicate with the CPU. Now, memory and graphics card communicate with the CPU within the same package, thereby relieving much of the bandwidth between the processor and the PCH. This means that the PCH is not connected to the memory or the PCI-Express graphics (PEG) slot. However, the PCH still does have a display controller and a connection to the integrated graphics display if one exists. In addition, the system clock is not a connection any longer and instead fused in with the PCH. Two different connections exist between the PCH and the CPU: Flexible Display Interface (FDI) and Direct Media Interface (DMI). The FDI only exists if an integrated graphics device (IGD) is in the CPU package.

Ibex Peak

Platform Controller Hub Based Chipset Architecture Block Diagram

The Intel 5 Series chipsets were the first to introduce a PCH. This first PCH is codenamed Ibex Peak.

This has the following variations:

• BD3400 (PCH 3400) Server
• BD3420 (PCH 3420) Server
• BD3450 (PCH 3450) Server
• BD82P55 (PCH P55) Desktop Base
• BD82H55 (PCH H55) Desktop Home
• BD82H57 (PCH H57) Desktop Home
• BD82Q57 (PCH Q57) Desktop Office
• BD82PM55 (PCH PM55) Mobile Base
• BD82HM55 (PCH HM55) Mobile Home
• BD82HM57 (PCH HM57) Mobile Home
• BD82QM57 (PCH QM57) Mobile Office
• BD82QS57 (PCH QS57) Mobile SFF

Issues

• USB ports hang with bulk and control traffic (erratum 7 & Microsoft KB982091[1])
• Bogus USB ports will be detected at desktop PCH equipped with 6 USB ports (3420, H55) on the first EHCI controller. This can happen when AC power is removed after entering ACPI S4. Adding AC power back and resuming from S4 may result in non detected or even non functioning USB device (erratum 12)
• Bogus USB ports will be detected at mobile PCH equipped with 6 USB ports (HM55) on the first EHCI controller. This can happen when AC power and battery are removed after entering ACPI S4. Adding AC power or battery back and resuming from S4 may result in non detected or even non functioning USB device (erratum 13)
• Reading the HPET comparator timer immediately after a write, returns the old value (erratum 14)
• SATA 6Gb/s devices may not be detected at cold boot or after ACPI S3, S4 resume (erratum 21)

Langwell

Langwell is the codename of a PCH in the Moorestown MID platform chipset.^[1][2] for Atom Lincroft microprocessors.

This has the following variations:

• AF82MP20 (PCH MP20)
• AF82MP30 (PCH MP30)

Tiger Point

Tiger Point is the codename of a PCH in the Pine Trail netbook platform chipset for Atom Pineview microprocessors.

This has the following variations:

• CG82NM10 (PCH NM10)

Topcliff

Topcliff is the codename of a PCH in the Queens Bay embedded platform chipset for Atom Tunnel Creek microprocessors.

It connects to the processor via PCI-E (vs. DMI as other PCHs do).

This has the following variations:

• CS82TPCF (PCH EG20T)

Cougar Point

Cougar Point is the codename of a PCH in Intel 6 Series chipsets for mobile and desktop (and possibly later workstation/server) platforms. It is most closely associated with Sandy Bridge processors.

This has the following variations:

• BD82C202 (PCH C202) Server
• BD82C204 (PCH C204) Server
• BD82C206 (PCH C206) Workstation / Server
• BD82P67 (PCH P67) Desktop Base
• BD82H67 (PCH H67) Desktop Home
• BD82H61 (PCH H61) Desktop Home
• BD82Z68 (PCH Z68) Combined desktop base and home
• BD82B65 (PCH B65) Desktop Office
• BD82Q67 (PCH Q67) Desktop Office
• BD82HM65 (PCH HM65) Mobile Home
• BD82HM67 (PCH HM67) Mobile Home
• BD82QM67 (PCH QM67) Mobile Office
• BD82QS67 (PCH QS67) Mobile SFF
• BD82UM67 (PCH UM67) Ultra Mobile

Issues

In the first month of Cougar Point's release, January 2011, Intel posted a press release stating a design error had been discovered.^[3] Specifically, a transistor in the 3 Gbps PLL clocking tree was receiving too high voltage.^[4] The projected result was a 5–15% failure rate within three years of 3 Gbps SATA ports, commonly used for storage devices such as hard drives and DVD drives. Through OEMs, Intel plans to repair or replace all affected products at a cost of $700 million.

Whitney Point

Whitney Point is the codename of a PCH in the Oak Trail platform chipset for Atom Lincroft microprocessors.

This has the following variations:

• 82SM35 (PCH SM35)

Panther Point

According to Intel roadmaps,^[5] the next PCH to replace Cougar Point will be Panther Point and will be paired with Ivy Bridge processors. This chipset will have integrated USB 3.0^[6]

Future

The Intel X58 Tylersburg based platform will likely be replaced by Waimea Bay which includes a Sandy Bridge-E CPU and an X79 Patsburg PCH.^[7][8]

See also

• List of Intel chipsets
• System Controller Hub (SCH)
• I/O Controller Hub (ICH)
• PCI IDE ISA Xcelerator (PIIX)

References

1. ^ Langwell Background Information, Intel Corporation, http://ark.intel.com/ProductCollection.aspx?codeName=29964, retrieved 2010-08-03 
2. ^ New Intel® Atom™ Processor-Based Platform Using Significantly Lower Power Readies Intel for Smartphone, Tablet Push, Intel Corporation, May 4, 2010, http://www.intel.com/pressroom/archive/releases/20100504comp.htm, retrieved 2010-07-27 
3. ^ Intel Identifies Chipset Design Error, Implementing Solution, Intel, 31 January 2011, http://newsroom.intel.com/community/intel_newsroom/blog/2011/01/31/intel-identifies-chipset-design-error-implementing-solution 
4. ^ The Source of Intel's Cougar Point SATA Bug, AnandTech, 31 January 2011, http://www.anandtech.com/show/4143/the-source-of-intels-cougar-point-sata-bug 
5. ^ Data CenterGroup (DCG) Channel Roadmap, http://www.thegioimaychu.vn/ntc/intel/intel-082010.pdf 
6. ^ http://www.anandtech.com/show/4406/correction-ivy-bridge-and-thunderbolt-featured-not-integrated
7. ^ A Look Into Intel's Next Gen Enthusiast Platform : Sandy Bridge E & Waimea Bay, VR-Zone, April, 15 2010, http://vr-zone.com/articles/a-look-into-intel-s-next-gen-enthusiast-platform--sandy-bridge-e--waimea-bay/8877.html, retrieved 2010-07-27 
8. ^ Intel X58接班人：X79官方规格全曝光-Intel,X58,X79,LGA2011,Sandy Bridge-E,SNB-E-驱动之家, mydrivers.com, 2011-03-30, http://news.mydrivers.com/1/189/189790.htm, retrieved 2011-04-17