32 nanometer

The 32 nanometer (32 nm) process (also called 32 nanometer node) is the next step after the 45 nanometer process in CMOS manufacturing and fabrication. "32 nm" refers to the expected average half-pitch of a memory cell at this technology level. The two major chip rivals, Intel and AMD, are both working on a 32 nanometer process for logic, which uses significantly looser design rules. [ Y. Borodovsky," Marching to the Beat of Moore's Law, SPIE 2006. ] AMD has partnered with IBM on this process, as it did with the 45 nm process. IBM will release the 32 nm process for prototyping designs with the Common Platform in the third quarter of 2008, [ [http://www.semiconductor.net/article/CA6551303.html?desc=topstory Semiconductor International article on IBM alliance offering 32 nm process technology to customers for initial prototyping in Q3 2008] ] while Intel will begin its 32 nm production later in 2009. [ [http://www.eetimes.com/news/latest/showArticle.jhtml;jsessionid=3UWFVDNZFWTTMQSNDLQCKH0CJUNN2JVN?articleID=208803035 EETimes article on Intel's 32 nm lithography vendor decision] ]

Technology demos

IMEC (Belgium) has recently [http://www.physorg.com/news80410095.html demonstrated] a 32 nm Flash patterning capability based on double patterning and immersion lithography. The introduction of double patterning may offset some of the cost advantages of moving from one node to the next, but may be unavoidable in order to reduce memory cell area.

TSMC similarly used double patterning combined with immersion lithography to produce a 32 nm node 0.183 square micrometer six-transistor SRAM cell in 2005. [ H-Y. Chen et al., Symp. on VLSI Tech. 2005.]

IBM demonstrated a 0.143 square micrometer SRAM cell, produced using electron-beam lithography and optical lithography on the same layer. It was observed that the static noise margin (sensitivity to input voltage fluctuations) degraded significantly in going to such a small SRAM cell size. The poly gate pitch was 135 nm. [ D. M. Fried et al., IEDM 2004.]

Intel showed the first 32nm test chips to the public on September 18, 2007 at the Intel Developer Forum. At the release, several technical details were disclosed. A second-generation high-k gate dielectric and metal gate were used. The cell size was 0.182 square micrometers and the chip contained almost 2 billion transistors. 193 nm immersion lithography was used for the critical layers, while 193 nm or 248 nm dry lithography was used on less critical layers.

IM Flash Technologies launched a 32 Gb NAND Flash built on 34 nm design rules in May 2008. This design rule could only be accomplished with double patterning using 193 nm lithography tools.

In late October 2007, Samsung disclosed a 30 nm NAND Flash patterning process, using self-aligned double patterning. Starting from a 60 nm half-pitch pattern, new material was deposited and etched in between features to produce a 30 nm half-pitch pattern. Presumably, this can be repeated once more for 15 nm half-pitch.

As of 2008, the use of double patterning for 32 nm lithography appears inevitable, due to the lack of availability of alternative lithography techniques which meet manufacturing targets (such as throughput).

The successors to 32 nm technology will be 22 nm, and then 16 nm technology [http://www.itrs.net/reports.html per ITRS] .

References

Other reading

*S. Steen et al., Microelec. Eng., vol. 83, pp. 754-761 (2006).

External links

* [http://news.com.com/Chipmakers+gear+up+for+manufacturing+hurdles/2100-1006_3-6082393.html Chipmakers gear up for manufacturing hurdles]
* [http://www.sony.net/SonyInfo/News/Press/200601/06-0112E/ Sony, IBM, and Toshiba partnering on semiconductor research]
* [http://www.pcworld.com/news/article/0,aid,117889,00.asp IBM and AMD partnering on semiconductor research]
* [http://hardware.slashdot.org/comments.pl?sid=189944&cid=15632847 Slashdot discussion]
* [http://www.intel.com/pressroom/archive/releases/20070918corp_a.htm Intel press release]
* [http://www.physorg.com/news109344893.html Intel 32 nm process]
* [http://download.intel.com/pressroom/kits/events/idffall_2007/BriefingSilicon&TechManufacturing.pdf Intel 32 nm SRAM demonstration at IDF 2007]
* [http://sst.pennnet.com/display_article/309943/5/ARTCL/none/none/1/Samsung-touts-30nm-NAND-flash-using-double-patterning/ Samsung self-aligned double patterning technology] sequence
prev=45 nm
next=22 nm
list=CMOS manufacturing processes