- 22 nanometer
The 22 nanometer (22 nm) node is the CMOS process step following 32 nm. It is expected to be reached by
semiconductor companies in the 2011–2012 timeframe. At that time, the typical half-pitch for a memory cell would be around 22 nm. The exact naming of this technology node comes from theInternational Technology Roadmap for Semiconductors (ITRS).The ITRS 2006 Front End Process Update indicates that equivalent physical oxide thickness will not scale below 0.5 nm which is the expected value at the 22 nm node. This is an indication that CMOS scaling in this area has reached a wall at this point.
Since the 32 nm half-pitch already requires using
double patterning , in conjunction with hyper-NA (numerical aperture )immersion lithography tools, this approach will continue to be used at the 22 nm half-pitch, to which it can be scaled. [ [http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=197008463 EEtimes article on 22 nm] ]Some predictions for the 22 nm node come from the ITRS. For example, it is predicted that silicon devices will no longer be planar, but will require ultrathin sections mostly surrounded on the sides by gates. The silicon body in each section is fully depleted, i.e., the free charge carrier concentration is deliberately suppressed. The sections basically protrude as fins from the surface (sometimes these are known as
FinFET s). The creation of fins is a new challenge for the semiconductor industry, which has become accustomed to building transistors on a flat silicon surface.According to the ITRS, the 22 nm node also marks the first time where the pre-metal dielectric, separating the transistor from the first metal layer, is a porous
low-k material, replacing traditional, denser CVD silicon dioxide. The introduction of a porous material closer to the front end presents numerous integration challenges. In particular, the extent of plasma damage to low-k materials is typically 20 nm thick, [ O. Richard "et al.", Microelectronic Engineering 84, pp. 517-523 (2007).] but can also go up to approximately 100 nm. [ T. Gross "et al.", Microelectronic Engineering 85, pp. 401-407 (2008).]The successor to 22 nm technology will be 16 nm technology [http://www.itrs.net/reports.html per ITRS] .
Technology Demos
On
August 18 2008 ,AMD ,Freescale ,IBM ,STMicroelectronics ,Toshiba and theCollege of Nanoscale Science and Engineering (CNSE) announced that they jointly developed and manufactured a 22 nmSRAM cell, built on a traditional six-transistor design on a 300 mm wafer, which had a memory cell size of just 0.1 squareμm . [ [http://www.tgdaily.com/content/view/38941/135/ TG Daily news report] ] The cell was printed usingimmersion lithography . [ [http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=210101316 EETimes news report] ]References
External links
* [http://www.fabtech.org/content/view/65552/ IBM planning 22nm photomask development with immersion lithography ]
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