Tejas and Jayhawk

Tejas was a code name for Intel's microprocessor which was to be a successor to the latest Pentium 4 with Prescott core. Jayhawk was a code name for its Xeon counterpart. The cancellation of the processors in May 2004 underscored Intel's historical transition of its focus on single-core processors to dual-core processors.

In early 2003, Intel showed the design of Tejas and a plan to release it sometime in 2004, but put it off to 2005 later. Intel, however, announced it canceled the development on May 7, 2004. Analysts attribute the delay and eventual cancellation to the heat problem due to the prodigious power consumption of the core, as that was the case in development of Prescott and its mediocre performance increase over Northwood. This cancellation reflected Intel's intention to focus on dual-core chips for the Itanium platform. With respect to desktop processors, Intel's development efforts shifted to the Pentium M micro-architecture (itself a derivative of the Pentium III micro-architecture) used in the Centrino notebook platform, which offered a processing power to power consumption ratio considerably higher than that offered by Prescott and other NetBurst based designs. The outcome of these development efforts was the Intel Core processor line, and later the Intel Core 2 line, providing and building on the benefits of Pentium M and offering Intel's first native dual core products for the desktop and laptop.

This transition marks the end of the NetBurst line of CPU development from Intel that started back with the original Pentium 4.

Design and microarchitecture

Tejas would have built on the Pentium 4's NetBurst microarchitecture. Tejas was to originally be built on a 90 nm process, later moving to a 65 nm process. The 90 nm version of the processor was reported to have 1 MB L2 cache, while the 65 nm chip would increase the cache to 2 MB. There was also to be a dual core version of Tejas called "Cedarmill" (or "Cedar Mill" depending on the source). This "Cedarmill" should not be confused with the 65 nm Pentium 4 Cedar Mill. The trace cache would likely have been increased, and the number of pipeline stages was increased to between 40 and 50 steps. [http://tweakers.net/reviews/740/chip-magicians-at-work-patching-at-45nm.html Chip magicians at work: patching at 45nm] ] There would have been an improved version of Hyper-Threading, as well as a new version of SSE, which was later backported to the Intel Core 2 series after Tejas's cancellation and named SSSE3. Tejas was slated to operate at frequencies of 7 GHz or higher which is more than twice as high as the clockspeed of a typical Core microarchitecture CPU which replaced it in the Intel lineup. However, Tejas would still have been slower because it would have executed fewer instructions per clock. The CPU was cancelled late in its development after it had reached its tapeout phase. [http://tweakers.net/reviews/740/chip-magicians-at-work-patching-at-45nm.html Chip magicians at work: patching at 45nm] ]

External links

* [http://www.nytimes.com/2004/05/08/business/08chip.html?ex=1399348800&en=98cc44ca97b1a562&ei=5007 The New York Times - Intel Halts Development of 2 New Microprocessors]
* [http://tweakers.net/reviews/740/chip-magicians-at-work-patching-at-45nm.html Chip magicians at work: patching at 45nm]

References