Memory type range register

Memory type range registers (MTRRs) are a set of processor supplementary capabilities control registers that provide system software with control of how accesses to memory ranges by the CPU are cached. It uses a set of programmable model-specific registers (MSRs) which are special registers provided by most modern CPUs.

Possible access modes to memory ranges can be:

• uncached
• write-through
• write-combining
• write-protect
• write-back

Additional bits which are provided on some computer architectures such as AMD64 allow the shadowing of ROM contents in system memory (Shadow ROM) and the configuration of memory-mapped I/O.

In write-back mode, writes are written to the CPU's cache and the cache is marked dirty, so that its contents are written to memory later.

Write-combining allows bus write transfers to be combined into a larger transfer before bursting them over the bus to allow more efficient writes to system resources like graphics card memory. This often increases the speed of image write operations by several times, at the cost of losing the simple sequential read/write semantics of normal memory.

MTRRs in x86-PC processors

In early x86 architecture systems, especially where the cache was provided by separate chips outside of the CPU package, this function was controlled by the chipset itself and configured through BIOS settings.

When the CPU cache was moved inside the CPU, the CPUs implemented fixed-range MTRRs ranges which cover the first mebibyte of memory to be compatible to what PC-BIOSes provided at that time. These are used to control the cache policy needed for VGA accesses and all other memory-accesses done while the system is in real mode. Above 1 MiB, CPUs provide a number of variable-range MTRRs, which can be freely placed and even overlap. These variable-range MTRRs can be used to set the caching policy of graphics memory and other memory ranges used by PCI devices.

Starting with the Intel P6 family of processors (Pentium Pro, Pentium II and later), MTRRs may be used to control the processor access to memory ranges^[1].

The Cyrix 6x86, 6x86MX and MII processors have Address Range Registers (ARRs) which provide a similar functionality to MTRRs.

The AMD K6-2 (stepping 8 and above) and K6-III processors have two MTRRs. The AMD Athlon family provide 8 Intel-style MTRRs.

The Centaur C6 WinChip has 8 MCRs, allowing write-combining.

The VIA Cyrix III and VIA C3 CPUs offer 8 Intel-style MTRRs.

The memory interface of AMD K8 CPUs supports "Extended fixed-range MTRR Type-Field Encodings" which allows one to specify whether accesses to certain address ranges are executed by accessing RAM through the Direct Connect Architecture or by executing memory-mapped I/O. This allows, for example, shadow RAM to be implemented by copying ROM contents into RAM.

Successor

Newer (primarily 64-bit) x86 CPUs support a more advanced technique called Page Attribute Tables that allow for per-table setting of these modes, instead of having a limited number of low-granularity registers to deal with modern memory sizes that can be as high as 8 GiB even on a laptop, and several times that amount on a desktop system.

Details on how MTRRs work are described in the processor manuals from CPU vendors.

See also

• Write barrier
• Page attribute table (PAT)
• Address-range register

References

1. ^ "The Linux Gamers' HOWTO". The Linux Gamers' HOWTO. tldp.org. http://tldp.org/HOWTO/Linux-Gamers-HOWTO/x343.html. Retrieved 2009-10-03. 

External links

• Speeding up graphics with MTRR includes explanation
• AMD64 Architecture Programmer's Manual Volume 2: System Programming (PDF)
• Intel 64 and IA-32 Architectures Software Developer's Manuals See Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A: System Programming Guide section 11.11 MEMORY TYPE RANGE REGISTERS (MTRRS)
• MTRRLFBE utility for DOS by RayeR - it can set caching modes for VGA and LFB memory range to significantly boost performance of DOS graphics apps. On modern Core 2 Duo PC with PCI-E VGA it can be 10-times faster when write combining is set.