DDR4 SDRAM

DDR4 SDRAM
This article is about DDR4 SDRAM. For graphics DDR4, see GDDR4.
The first DDR4 memory module was manufactured by Samsung and announced in January 2011.

In computing, DDR4 SDRAM, an abbreviation for double data rate type four synchronous dynamic random-access memory, is a type of dynamic random-access memory (DRAM) with a high bandwidth interface currently under development and expected market release in 2012. As a "next generation" successor to DDR3 SDRAM, it is one of several variants of DRAM used since the early 1970s.[citation needed] It is not directly compatible with any earlier type of random access memory (RAM) due to different signaling voltages, timings, physical interface and other factors.

DDR4 itself is a DRAM interface specification. Its primary benefits compared to DDR3 include a higher range of clock frequencies and data transfer rates (2133–4266 MT/s compared to DDR3's 800–2133[1][2]) and significantly lower voltage (1.2 - 1.05 V for DDR4,[2] compared to 1.5 – 1.2 V for DDR3). DDR4 also anticipates a change in topology – it discards dual and triple channel approaches in favor of point-to-point where each channel in the memory controller is connected to a single module.[2][3] Switched memory banks are also an anticipated option for servers.[2]

Contents

Development and market history

Standards body JEDEC began working on a successor to DDR3 around 2005,[4] about 2 years before the launch of DDR3 in 2007.[5][6] The high-level architecture of DDR4 was planned for completion in 2008 and, as of 2007, was said by JEDEC's Future DRAM task group chairman to be "on time".[7] The final specification is expected in the second half of 2011,[8] shortly before DDR4's commercial launch.[8] Some advance information was published in 2007,[9] and a guest speaker from Qimonda provided further public details in a presentation at the August 2008 San Francisco Intel Developer Forum (IDF).[10][9][11][12] DDR4 was described as involving a 30 nm process at 1.2 volts, with bus frequencies of 2133 MT/s "regular" speed and 3200 MT/s "enthusiast" speed, and reaching market in 2012, before transitioning to 1 volt in 2013.[12][10]

Subsequently, further details were revealed at MemCon 2010, Tokyo (a computer memory industry event), at which a presentation by a JEDEC director titled "Time to rethink DDR4" [13] with a slide titled "New roadmap: More realistic roadmap is 2015" led some websites to report that the introduction of DDR4 was probably[14] or definitely[15][16] delayed until 2015. However, DDR4 test samples were announced in line with the original schedule in early 2011 at which time manufacturers began to advise that large scale commercial production and release to market was scheduled for 2012.[8]

DDR4 is expected to represent 5% of the DRAM market in 2013,[8] and to reach mass market adoption and 50% market penetration around 2015;[8] the latter is comparable with the approximately 5 years taken for DDR3 to achieve mass market transition over DDR2.[2] In part, this is because changes required to other components would impact all other parts of computer systems, which would need to be updated to work with DDR4.[1]

In February 2009, Samsung validated 40 nm DRAM chips, considered a "significant step" towards DDR4 development[17] since in 2009, DRAM chips were only beginning to migrate to a 50 nm process.[18] In January 2011, Samsung announced the completion and release for testing of a 2 GB DDR4 DRAM module based on a process between 30 and 39 nm.[19] It has a maximum data transfer rate of 2133 Mb/s at 1.2 V, uses pseudo open drain technology (adapted from graphics DDR memory[20]) and draws 40% less power than an equivalent DDR3 module.[21][22][19]

Three months later in April 2011, Hynix announced the production of 2 GB DDR4 modules at 2400 MT/s, also running at 1.2 V on a process between 30 and 39 nm (exact process unspecified),[8] adding that it anticipated commencing high volume production in the second half of 2012.[8] Semiconductor processes for DDR4 are expected to transition to sub-30 nm at some point between late 2012 and 2014.[2][23]

Technical description

The new chips are expected to run at 1.2 V or less,[24][25] versus the 1.5 V of DDR3 chips, and have in excess of 2 billion data transfers per second. They are expected to be introduced at clock speeds of 2133 MT/s, estimated to rise to a potential 4266 MT/s [1] and lowered voltage of 1.05 V [26] by 2013. DDR4 is likely to be initially commercialized using 32 – 36 nm processes,[1] and according to a roadmap by PC Watch (Japan) and comments by Samsung, as 4 Gbit chips.[23][19] Increased memory density was also anticipated, possibly using TSV ("through-silicon via") or other 3D stacking processes.[3][1][2][27] The DDR4 specification will include standardized 3D stacking "from the start" according to JEDEC.[27] X-bit Labs commented that "as a result DDR4 memory chips with very high density will become relatively inexpensive".[1] Prefetch an 8n prefetch with bank groups, including the use of two or four selectable bank groups.[28]

DDR4 also anticipates a change in topology. It discards dual and triple channel approaches (used since the original first generation DDR[29]) in favor of point-to-point where each channel in the memory controller is connected to a single module.[2][3] This mirrors the trend also seen in the earlier transition from PCI to PCI Express, where parallelism was moved from the interface to the controller,[3] and is likely to simplify timing in modern high-speed data buses.[3] Switched memory banks are also an anticipated option for servers.[2][3]

The minimum clock speed of 2133 MT/s was said to be due to progress made in DDR3 speeds which, being likely to reach 2133 Mb/s, left little commercial benefit to specifying DDR4 below this speed.[1][2] Techgage interpreted Samsung's January 2011 engineering sample as having CAS latency of 13 clock cycles, described as being comparable to the move from DDR2 to DDR3.[20]

In 2008, concerns were raised in the book Wafer Level 3-D ICs Process Technology that non-scaling analog elements such as charge pumps and voltage regulators, and additional circuitry "have allowed significant increases in bandwidth but they consume much more die area". Examples include CRC error-detection, on-die termination, burst hardware, programmable pipelines, low impedence, and increasing need for sense amps (attributed to a decline in bits per bitline due to low voltage). The authors noted that as a result, the amount of die used for the memory array itself has declined over time from 70-80% with SDRAM and DDR1, to 38% for DDR3 and potentially to less than 30% for DDR4.[30]

References

  1. ^ a b c d e f g Shilov, Anton (August 16, 2010). "Next-Generation DDR4 Memory to Reach 4.266GHz – Report". Xbitlabs.com. http://www.xbitlabs.com/news/memory/display/20100816124343_Next_Generation_DDR4_Memory_to_Reach_4_266GHz_Report.html. Retrieved 2011-01-03. 
  2. ^ a b c d e f g h i j 後藤 弘茂 ("Gotou Shigehiro"). "メモリ4Gbps時代へと向かう次世代メモリDDR4 ("Towards Next-Generation 4Gbps DDR4 Memory")". 2010-08-16. PC Watch (Japan). http://pc.watch.impress.co.jp/docs/column/kaigai/20100816_387444.html. Retrieved 2011-04-25.  (English translation)
  3. ^ a b c d e f Swinburne, Richard (2010-08-26). "DDR4: What we can Expect". bit-tech.net. http://www.bit-tech.net/hardware/memory/2010/08/26/ddr4-what-we-can-expect/1. Retrieved 2011-04-28.  – Page 1 – Page 2 – Page 3
  4. ^ Sobolev, Vyacheslav (2005-05-31). "JEDEC: Memory standards on the way". digitimes.com. http://www.digitimes.com/news/a20050530PR201.html. Retrieved 2011-04-28. "Initial investigations have already started on memory technology beyond DDR3. JEDEC always has about three generations of memory in various stages of the standardization process: current generation, next generation, and future." 
  5. ^ "DDR3: Frequently asked questions". Kingston Technology. http://www.kingston.com/channelmarketingcenter/hyperx/literature/MKF_1223-1_DDR3_FAQ.pdf. Retrieved 2011-04-28. ""DDR3 memory launched in June 2007"" 
  6. ^ Valich, Theo (2007-05-02). "DDR3 launch set for May 9th". The Inquirer. http://www.theinquirer.net/inquirer/news/1016272/ddr3-launch-set-may-9th. Retrieved 2011-04-28. 
  7. ^ Hammerschmidt, Christoph (2007-08-29). "Non-volatile memory is the secret star at JEDEC meeting". eetimes.com. http://www.eetimes.com/electronics-news/4189215/Non-volatile-memory-is-the-secret-star-at-JEDEC-meeting?pageNumber=1. Retrieved 2011-04-28. 
  8. ^ a b c d e f g "Hynix produces its first DDR4 modules". behardware.com. 2011-04-05. http://www.behardware.com/news/11425/hynix-produces-its-first-ddr4-modules.html. Retrieved 2011-04-26. 
  9. ^ a b "DDR4 – the successor to DDR3 memory". The "H" (h-online.com). 2008-08-21. http://www.h-online.com/newsticker/news/item/IDF-DDR4-the-successor-to-DDR3-memory-736983.html. Retrieved 2011-04-28. "The JEDEC standardisation committee cited similar figures around one year ago" 
  10. ^ a b Graham-Smith, Darien (2008-08-19). "IDF: DDR3 won't catch up with DDR2 during 2009". PC Pro. http://www.pcpro.co.uk/news/220257/idf-ddr3-wont-catch-up-with-ddr2-during-2009. Retrieved 2011-04-28. 
  11. ^ Volker Risska (Volker Rißka) (2008-08-21). "IDF: DDR4 als Hauptspeicher ab 2012 ["Intel Developer Forum: DDR4 as the main memory from 2012""]. computerbase.de. http://www.computerbase.de/news/hardware/arbeitsspeicher/2008/august/idf-ddr4-als-hauptspeicher-ab-2012/. Retrieved 2011-04-28.  (English)
  12. ^ a b Novakovic, Nebojsa (2008-08-19). "Qimonda: ddr3 moving forward". The Inquirer. http://www.theinquirer.net/inquirer/news/1012591/qimonda-ddr3-moving-forward. Retrieved 2011-04-28. 
  13. ^ Gervasi, Bill. "Time to rethink DDR4". July 2010. Discobolus Designs. http://discobolusdesigns.com/personal/20100721a_gervasi_rethinking_ddr4.pdf. Retrieved 2011-04-29. 
  14. ^ "DDR4-Speicher kommt wohl später als bisher geplant ("DDR4 memory is probably later than previously planned")". heise.de. 2010-08-17. http://www.heise.de/newsticker/meldung/DDR4-Speicher-kommt-wohl-spaeter-als-bisher-geplant-1060545.html. Retrieved 2011-04-29.  (English)
  15. ^ Nilsson, Lars-Göran (2010-08-16). "DDR4 not expected until 2015". semiaccurate.com. http://semiaccurate.com/2010/08/16/ddr4-not-expected-until-2015/. Retrieved 2011-04-29. 
  16. ^ By 'annihilator' (2010-08-18). "DDR4 memory in Works, Will reach 4.266GHz". wccftech.com. http://wccftech.com/2010/08/18/ddr4-memory-works-reach-4266ghz/. Retrieved 2011-04-29. 
  17. ^ Gruener, Wolfgang (February 4, 2009). "Samsung hints to DDR4 with first validated 40 nm DRAM". tgdaily.com. http://www.tgdaily.com/content/view/41316/139/. Retrieved 2009-06-16. 
  18. ^ Jansen, Ng (January 20, 2009). "DDR3 Will be Cheaper, Faster in 2009". dailytech.com. http://www.dailytech.com/DDR3+Will+be+Cheaper+Faster+in+2009/article13977.htm. Retrieved 2009-06-17. 
  19. ^ a b c "Samsung Develops Industry's First DDR4 DRAM, Using 30nm Class Technology". Samsung. 2011-04-11. http://www.samsung.com/us/business/semiconductor/newsView.do?news_id=1202. Retrieved 26 April 2011. 
  20. ^ a b Perry, Ryan (2011-01-06). "Samsung Develops the First 30nm DDR4 DRAM". techgage.com. http://techgage.com/news/samsung_develops_the_first_30nm_ddr4_dram/. Retrieved 2011-04-29. 
  21. ^ "Samsung Develops Industry's First DDR4 DRAM, Using 30nm Class Technology". Samsung. 2011-01-04. http://www.samsung.com/us/business/semiconductor/newsView.do?news_id=1202. Retrieved 2011-03-13. 
  22. ^ http://www.techspot.com/news/41818-samsung-develops-ddr4-memory-up-to-40-more-efficient.html
  23. ^ a b "Diagram: Anticipated DDR4 timeline". 2010-08-146. PC Watch (Japan). http://translate.googleusercontent.com/translate_c?hl=en&ie=UTF-8&sl=ja&tl=en&u=http://pc.watch.impress.co.jp/img/pcw/docs/387/444/html/kaigai-09.jpg.html&prev=_t&rurl=translate.google.com&twu=1&usg=ALkJrhiDMjWRSrDnnnL4mro50bRDlxQlVw. Retrieved 2011-04-25.  (Linked from cited PC Watch article dated Aug 16 2010)
  24. ^ Looking forward to DDR4
  25. ^ DDR3 successor
  26. ^ "IDF: DDR4 memory targeted for 2012" (in German). hardware-infos.com. http://www.hardware-infos.com/news.php?news=2332. Retrieved 2009-06-16.  English translation
  27. ^ a b "JEDEC Announces Broad Spectrum of 3D-IC Standards Development". JEDEC. 2011-03-17. http://www.jedec.org/news/pressreleases/jedec-announces-broad-spectrum-3d-ic-standards-development. Retrieved 26 April 2011. 
  28. ^ "Main Memory: DDR3 & DDR4 SDRAM". jedec.org. http://www.jedec.org/category/technology-focus-area/main-memory-ddr3-ddr4-sdram. Retrieved 2011-09-29. 
  29. ^ See for example
  30. ^ Tan, Gutmann and Reif (2008). Wafer Level 3-D ICs Process Technology. Springer. pp. 278 (sections 12.3.4 – 12.3.5). http://books.google.com/books?id=fhen8HeoC1AC&pg=PA278&dq=ddr4+sdram&hl=en&ei=iLa2Ta6LAY_Cswa1m9DNDQ&sa=X&oi=book_result&ct=result&resnum=13&ved=0CIcBEOgBMAw#v=onepage&q=ddr4%20sdram&f=false. 

See also

v · d · eTypes of DRAM
Asynchronous
FPM RAM · EDO RAM
Synchronous
SDRAM · DDR SDRAM · Mobile DDR (LPDDR) · DDR2 SDRAM · DDR3 SDRAM · DDR4 SDRAM
Graphics
EDO · VRAM · WRAM · MDRAM · SGRAM · SDRAM · DDR · DDR2 · GDDR3 · GDDR4 · DDR3 · GDDR5
Rambus

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