- DLX
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For other uses, see DLX (disambiguation).
DLX Designer John L. Hennessy and David A. Patterson Bits 32-bit Design RISC Registers 32 The DLX is a RISC processor architecture designed by John L. Hennessy and David A. Patterson, the principal designers of the MIPS and the Berkeley RISC designs (respectively), the two benchmark examples of RISC design. The DLX is essentially a cleaned up and simplified MIPS, with a simple 32-bit load/store architecture. Intended primarily for teaching purposes, the DLX design is widely used in university-level computer architecture courses.
In the original MIPS design one of the methods used to gain performance was to force all instructions to complete in one cycle, forcing the compiler to insert "no-ops" in cases where the instruction would definitely take longer, as in memory access for instance. In the DLX design a more modern approach to long instructions was used, using a data-forwarding system and reordering instructions. In this case the longer instructions are "stalled" in their functional units, and then re-inserted into the instruction stream when they do complete. Externally it appears execution occurred linearly.
DLX instructions can be broken down into three types, R-type, I-type and J-type. R-type instructions are pure register instructions, with three register references contained in the 32-bit word. I-type instructions specify two registers, and use 16 bits to hold an immediate value. Finally J-type instructions are jumps, containing a 26-bit address.
Opcodes are 6 bits long, for a total of 64 possible basic instructions. 5 bits are needed to select one of 32 registers. In the case of R-type instructions this means that only 21 bits of the 32-bit word are used, which allows the lower 6 bits to be used as "extended instructions". This allows the DLX to support more than 64 instructions, as long as those instructions work purely on registers. This is useful for things like FPU support.
The DLX, like the MIPS design, bases its performance on the use of an instruction pipeline. In the DLX design this is a fairly simple one, "classic" RISC in concept. The pipeline contains five stages:
- IF - Instruction Fetch unit
- reads instruction word from instruction stream based on program counter
- ID - Instruction Decode unit
- this unit gets instruction from IF, and extracts opcode and operand from that instruction. It also retrieves register values if requested by the operation.
- EX - Execution unit
- runs the instructions, typically referred to as the ALU in modern terminology
- MEM - Memory access unit
- the MEM unit fetches data from main memory, under the control of the instructions from ID and EX.
- WB - WriteBack unit
- typically referred to as "the store unit" in modern terminology.
See also
References
- Sailer, Philip M.; Kaeli, David R.. The DLX Instruction Set Architecture Handbook. Morgan Kaufmann. ISBN 1-55860-371-9.
- Hennessy Patterson, Jhon, David. Computer Organization and Design - The Hardware Software Interface. Morgan Kaufmann. ISBN 978-1558603295.
External links
RISC-based processor architectures Altera Nios II · AMD 29000 · Apollo PRISM · Analog Devices Blackfin · ARM · Atmel AVR · Atmel AVR32 · Cambridge Consultants XAP · DEC Alpha · DLX · eSi-RISC · PA-RISC · Intel i960 · M32R · LatticeMico8 · LatticeMico32 · MIPS · Motorola 88000 · OpenRISC · Power ISA · S+core · SPARC · Renesas SuperH · Xilinx MicroBlaze · Xilinx Picoblaze · XMOS XCore XS1Categories:- Educational abstract machines
- Instruction set architectures
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