Multiple patterning

Multiple patterning

Multiple patterning is a class of technologies developed for photolithography to enhance the feature density. The simplest case of multiple patterning is double patterning, where a conventional lithography process is enhanced to produce double the expected number of features. The resolution of a photoresist pattern begins to blur at around 45 nm half-pitch.[1] For the semiconductor industry, therefore, double patterning was introduced for the 32 nm half-pitch node and below, mainly using state-of-the-art 193 nm immersion lithography tools.

There are several types of double patterning. In combination, these may be used for multiple patterning.[2]


Dual-tone photoresist

Dual-tone photoresist: The lowest and highest doses of a single exposure result in insolubility, while the intermediate doses allow the photoresist to be removed by developer.

Dual-tone photoresists have been developed years ago, allowing the printing of two lines in a single exposure imaging of a single line. Early demonstrations relied on crosslinking of the highest dose regions, rendering them insoluble in developer, while the lowest dose regions were normally insoluble already.[3] Alternatively, a photobase generator may generate acid quenchers at high doses; the acid quenching counters their ability to render the photoresist soluble.[4][5] The simplicity and cost-effectiveness of this approach make it compelling as a method of extending current photolithographic capability. However, due to its inherent edge-printing characteristic, loops will generally be formed, which will need to be addressed by other process steps. In addition, the expected acid or base diffusion may limit the resolution of this technique.

Dual-Tone Development

Dual-tone development.Two develop steps remove highest and lowest exposure dose regions of the photoresist, leaving the intermediate dose edges.

Dual-tone development, such as Fujifilm's double development process,[6] is similar to the dual-tone photoresist technique above in that it doubles features without additional exposure. Instead the photoresist is developed twice; the first time by conventional developer which removes the high exposure dose areas, the second time by a different organic solvent which removes the unexposed or lowest exposure dose areas. This leaves the intermediate dose areas (normally defining the two feature edges) standing. A key challenge is to not only show successful positive and negative tone development process windows, but also to ensure the windows overlap sufficiently. Up to now, the successful overlap has only been shown in simulations rather than experimentally.

Self-aligned spacer

Spacer mask: first pattern; deposition; spacer formation by etching; first pattern removal; etching with spacer mask; final pattern

A spacer is a film layer formed on the sidewall of a pre-patterned feature. A spacer is formed by deposition or reaction of the film on the previous pattern, followed by etching to remove all the film material on the horizontal surfaces, leaving only the material on the sidewalls. By removing the original patterned feature, only the spacer is left. However, since there are two spacers for every line, the line density has now doubled. The spacer technique is applicable for defining narrow gates at half the original lithographic pitch, for example.

The spacer approach is unique in that with one lithographic exposure, the pitch can be halved indefinitely with a succession of spacer formation and pattern transfer processes. This conveniently avoids the serious issue of overlay between successive exposures. The spacer lithography technique has most frequently been applied in patterning fins for FinFETs.

As spacer materials are commonly hardmask materials, their post-etch pattern quality tends to be superior compared to photoresist profiles after etch, which are generally plagued by line edge roughness.[7]

The main issues with the spacer approach are whether the spacers can stay in place after the material to which they are attached is removed, whether the spacer profile is acceptable, and whether the underlying material is attacked by the etch removing the material attached to the spacer. Pattern transfer is complicated by the situation where removal of the material adjacent to the spacers also removes a little of the underlying material. This results in higher topography on one side of the spacer than the other.[8]

The positioning of the spacer also depends on the pattern to which the spacer is attached. If the pattern is too wide or too narrow, the spacer position is affected. However, this would not be a concern for critical memory feature fabrication processes which are self-aligned.

Double/Multiple exposure

Double exposure: photoresist coating; first exposure; second exposure; development

Double exposure is a sequence of two separate exposures of the same photoresist layer using two different photomasks.[9] This technique is commonly used for patterns in the same layer which look very different or have incompatible densities or pitches. In one important case, the two exposures may each consist of lines which are oriented in one or the other of two usually perpendicular directions. This allows the decomposition of two-dimensional patterns into two one-dimensional patterns which are easier to print. This is the basis of DDL technology from Brion Technologies, a subsidiary of ASML.[10] The sum of the exposures cannot improve the minimum resolution limit unless the photoresist response is not a simple addition of the two exposures. The double exposure technique allows manufacturability of minimum pitch features in a layout that may contain a variety of features. The 65 nm node saw the introduction of alternating phase-shift masks in manufacturing.[11] This technology is typically a double exposure approach. As long as double exposure can be used effectively and is kept within alignment tolerances, it is the preferred patterning approach since it does not require additional follow-up process steps.

Direct-write electron-beam lithography is inherently a multiple exposure technique, as the beam is shaped and projected onto the resist at multiple locations.

Double Expose, Double Etch (mesas)

Double Expose, Double Etch (lines): Photoresist coating over first pattern; photoresist features between previous features; etching; mask removal

This is best described by considering a process example. A first exposure of photoresist is transferred to an underlying hardmask layer. After the photoresist is removed following the hardmask pattern transfer, a second layer of photoresist is coated onto the sample and this layer undergoes a second exposure, imaging features in between the features patterned in the hardmask layer. The surface pattern is made up of photoresist features edged between mask features, which can be transferred into the final layer underneath. This allows a doubling of feature density. The Interuniversity Microelectronics Centre (IMEC, Belgium) recently used this approach to pattern the gate level for its 32 nm half-pitch demonstration.[12]

A concern with the use of this approach is the discrepancy and delay between the second photoresist pattern and the first hardmask pattern, resulting in an additional source of variation.

A variation on this approach which eliminates the first hardmask etch is resist freezing, which allows a second resist coating over the first developed resist layer. JSR has demonstrated 32 nm lines and spaces using this method, where the freezing is accomplished by surface hardening of the first resist layer.

Double Expose, Double Etch (trenches)

Double Expose, Double Etch (trenches): Photoresist coating over first pattern; etching adjacent to previous features; mask removal

A "brute force" approach for patterning trenches involves a sequence of (at least) two separate exposures and etchings of independent patterns into the same layer. For each exposure, a different photoresist coating is required. When the sequence is completed, the pattern is a composite of the previously etched subpatterns. By interleaving the subpatterns, the pattern density can theoretically be increased indefinitely, the half-pitch being inversely proportional to the number of subpatterns used. For example, a 25 nm half-pitch pattern can be generated from interleaving two 50 nm half-pitch patterns, three 75 nm half-pitch patterns, or four 100 nm half-pitch patterns. The feature size reduction will most likely require the assistance of techniques such as chemical shrinks, thermal reflow, or shrink assist films. This composite pattern can then be transferred down into the final layer.

A possible application would be, for example, dividing the contact layer into two separate groups: gate contacts and source/drain contacts, each defining its own mask. IMEC recently used an approach like this to demonstrate a 45 nm node 6-transistor SRAM cell using dry lithography [1].

As with the double-expose, double-etch mesas approach, any discrepancy among the different interleaved patterns would be a source of feature-to-feature variation.

Multiple patterning - the ultimate resolution

Feature quadrupling with second spacer patterning: 1st spacer deposition; 1st spacer etch; 1st and 2nd support material etch; 2nd spacer deposition; 2nd spacer etch; 2nd support material etch

The extrapolation of double patterning to multiple patterning has been contemplated, but the issue of cost control is still on the minds of many. While the benefits of multiple patterning in terms of resolution, depth of focus and lithographic defect sensitivity are understood, there is added burden to control the process budget increase and maintain good yield.

Beyond double (2X) patterning, the most frequently published multiple patterning methodology is the repeated spacer approach, which can be practiced in many forms.[13][14][15][16][17] A multilayer-on-topography spacer-type approach also offers some flexibility.[18] It is also possible to additively combine two or more of the above approaches. For example, a dual-tone photoresist with pitch-halved acid profile, plus dual-tone development that dissolves the highest and lowest acid concentrations, combined with a spacer process, would result in 8x pitch resolution enhancement,e.g., 40 nm half-pitch reduced to 5 nm half-pitch. Subsequently repeating the spacer process would give 16 x pitch resolution improvement, e.g., 40 nm half-pitch reduced to 2.5 nm half-pitch. The European LENS (Lithography Enhancement Towards Nano Scale) project[19] is targeted toward implementation of both double exposure (resist freezing) and spacer-based process, in principle enabling two ways of patterning for ~20 nm design rules with current lithography tools, already tailored for double patterning[20] or ~10 nm design rules in combination.[21] With successful dual-tone development of a dual-tone photoresist, 2.5 nm design rules can be imagined.

Intel used several spacer deposition/etch/clean steps to demonstrate spacers spaced apart by ~26 nm.[22] It represents a reduction of the original patterned pitch by a factor of ~1/4 and indicates that wavelength and optics no longer purely determine the lithographic resolution.

IMEC has indicated that in the event that EUV lithography is not ready, quadruple patterning (with tighter overlay specifications) would be used.[23]

At the 2010 Flash Memory Summit, it was projected that immersion lithography with multiple patterning would be used to scale NAND Flash to below 20 nm within a few years.[24]

2D layout considerations

For 2D patterns the density increase is very dependent on the nature of the pattern. For instance, contacts arrays have optimal packing density as rectangular arrays for double patterning but as hexagonal close packed arrays for triple patterning - achieving a close to 2 and 3 times area improvement respectively. For 2D layouts double patterning compliance errors occur when there are odd cycles of minimum spaces. This can be resolved by relaxing one of these spaces to a distance where both features can be patterned in the same imaging step. Triple patterning is compliant with odd cycles but in turn is non-complaint for two facing pairs of line-ends where the corner to corner space is below the single patterning distance. This in turn is compliant under quadruple patterning. The improvement in density with the use of multiple patterning schemes is thus highly dependent on the pattern. Often simple redesigns or relaxation of dimensions in one direction can avoid the expense of going to more complex and expensive multiple patterning processes.[25]

Synopsys has begun consideration of triple patterning decomposition of layers which are less easy to split into two patterns, such as contact layers.[26] While only increasing the number of processing steps by 50% (compared to 100% for the insertion of double patterning), triple patterning would enable 16 nm node patterning on a 45 nm node lithography tool. Likewise, quadruple patterning would enable 11 nm node patterning on the same 45 nm node lithography tool, with only 33% additional steps over triple patterning.


Due to its rather straightforward application, without the need to change the infrastructure, multiple patterning is not expected to encounter any insurmountable technical or commercialization barriers. Despite the cost and throughput concerns, it has recently received more attention and interest, mainly due to delays in next-generation lithography techniques such as EUVL and nanoimprint lithography.

Multiple patterning can also exploit high-bias processes (for example, photoresist trimming to reduce linewidth, or photoresist reflow to reduce trench width) to substantially eliminate defects sized at around 2x the design pitch or smaller. This is a significant advantage over increasing lithography tool resolution, which exposes the wafer to more defects at the design rule or even smaller.

Chip stacking of multiple dies

Stacking of multiple dies, e.g., DRAM in 3D-ICs,[27] requires patterning each die sequentially, as well as multiple instances of through-silicon via patterning.

Electron-beam lithography

As mentioned above, electron-beam lithography is inherently a multiple exposure technique. However, even electron beam lithography would eventually require at least two interleaved exposures (due to secondary electron scattering), for instance, in the fabrication of 15 nm half-pitch X-ray zone plates.[28] In fact, double patterning may not even be sufficient for sub-12 nm half-pitch, even with electron beam lithography.[29][30] In that case, multiple patterning would be necessary.

The use of irregular breaks in regularly spaced lines allows arbitrary layouts but could incur multiple exposures as well as cumulative area penalty.
The use of regular breaks in regularly spaced lines allows a single exposure for the breaks as well as opportunity for reduced area penalty.

Tela Innovations

Tela Innovations, a startup founded in 2005 which has recently garnered significant support and funding, specializes in converting arbitrary layouts into array-like features suitable for double patterning.[31] Tela Innovations achieves this by using gridded layouts (see Figures).


Intel has been using double patterning in its 45 nm as well as its 65 nm technology.[32][33] Double patterning is used to square off the ends of the transistor gates. The first mask pattern consists of the gate lines linked at the end. The second mask is a line cutter that separates these into separate gates, using a second photoresist coating.[34] The extra steps for the 45 nm double patterning compared to 65 nm are necessary due to the use of dry instead of immersion lithography.

In September 2009, Intel disclosed that for its 15 nm process, EUV did not appear to be ready in timely fashion.[35] Hence, Intel is preparing to extend 193 nm immersion lithography with double and possibly triple patterning to 15 nm.[36]

For its 11 nm logic node (20-22 nm half-pitch), Intel expects to be able to use quintuple exposure[37] with 193 nm lithography, where one of the exposures is used with spacer patterning for a further pitch division. The remaining four exposures are for cutting the pitch-divided lines. Even with a next-generation lithography like EUVL or maskless direct-write electron-beam lithography, a second exposure is still required for cutting. Referenced to its 32 nm node technology, the density is expected to be enhanced about 8x (three generations of doubling density), but the cost is less than 6x (5 exposures, with one round of spacer patterning).

Texas Instruments

At the 2010 Sematech Litho Forum, it was recommended by TI that for the 60 nm routed pitch layers, corresponding to the 22/20 nm node, double patterning“is the only economically feasible solution." Double and triple patterning was considered cost effective for die with a routed pitch of about 40nm.[38] For the 14nm node, triple patterning will be required for the gate, contact, and metal 1 layers. It was claimed that triple patterning at the 44 nm pitch provided a 25% better cost reduction.

NAND Flash Memory Makers

In 2010, IM Flash began producing 25 nm NAND Flash, with the combination of 193 nm immersion lithography and double patterning.[39]

Similar to the multiple patterning approach described for Intel's 11 nm process, in actual practice, NAND Flash memory array patterning using the spacer approach would use 3 or more mask exposures.[40] The first mask patterns the array core by defining the spacers, while a second mask is used to crop or trim the spacers to form individual lines. Lastly, additional masks or multiple patterning would be used to pattern peripheral connections, e.g., pads.[41] As a result, Flash memory patterning can generally be considered multiple patterning, not just a spacer-based double-patterning technique.

At IEDM 2011, Hynix is expected to report on a 15 nm NAND process, making use of, among other things, quadruple spacer patterning.[42]


  1. ^ T. Honda et al., J. Microlith., Microfab., Microsyst., Vol. 5, 043004 (2006).
  2. ^ C. Fonseca et al., Proc. SPIE vol. 7274, 72740I (2009).
  3. ^ U. S. Patent 6114082.
  4. ^ S. Song et al., Polymers for Adv. Tech. 9, 326-333 (1998).
  5. ^ X. Gu et al., J. Photopoly. Sci. & Tech. 22, 773-781 (2009).
  6. ^ K. Derbyshire, Solid State Technology, March 4, 2008.
  7. ^ X. Hua et al., J. Vac. Sci. Tech. B, vol. 24, pp. 1850-1858 (2006).
  8. ^ Y-K Choi et al., J. Phys. Chem. B, vol. 107, pp. 3340-3343 (2003).
  9. ^ See for example, US Patent 5308741.
  10. ^ Brion implements ASML' DDL Technology
  11. ^ A. Tritchkov, S. Jeong, and C. Kenyon, "Lithography Enabling for the 65 nm node gate layer patterning with Alternating PSM," Proc. SPIE vol. 5754, pp.215-225 (2005).
  12. ^ IMEC double patterning
  13. ^ A. Carlson and T-J. K. Liu, Proc. SPIE 6924, 69240B (2008).
  14. ^ B. Degroote et al., Microelec. Eng., 84, 609-618 (2007).
  15. ^ Y-K. Choi et al., Proc. SPIE 5220, 10 (2003).
  16. ^ US 6759180 
  17. ^ US 5328810 
  18. ^ US 7919413 
  19. ^ P. Cantu et al., Proc. SPIE 7640, 764022 (2010).
  20. ^ T. Castenmiller et al., Proc. SPIE 7640, 76401N (2010).
  21. ^ EETimes: IMFT 25-nm MLC NAND: technology scaling barriers broken, 3/22/2010
  22. ^ SEMICON West - Lithography Challenges and Solutions
  23. ^ EETimes "EUV litho keeps progressing, keeps slipping", 6/9/2010.
  24. ^ G. Tressler (IBM), 2010 Flash Memory Summit
  25. ^ B-S Seo et al, "Double Patterning addressing Imaging challenges for near and sub k1=0.25 node layouts", Proc. SPIE, Volume 7379, 73791N (2009).
  26. ^ C. Cork et al., Proc. SPIE, vol. 7028, 702839 (2008).
  27. ^ Elpida stacks four DDR3 DRAMs]
  28. ^ E. Anderson and W. Chao, Double exposure makes high-resolution diffractive optics, SPIE Newsroom, 2007.
  29. ^ W. Chao et al., JVST B 27, 2606-2611 (2009).
  30. ^ W. Chao et al., Proc. SPIE vol. 6883, 688309 (2008).
  31. ^ M. D. Levenson, "SPIE: Tela Innovations lays it all out straight", Microlithograpy World, Feb. 28 2008.
  32. ^ D. Vogler, Solid State Technology, Intel product launch event yields more insight into its manufacturing strategy
  33. ^ Intel Technology Journal June 17, 2008
  34. ^ Intel 45 nm process at IEDM
  35. ^ Semiconductor International 9/14/2009 Intel Ramping 32 nm Manufacturing in Oregon
  36. ^ EETimes 9/22/2009 Otellini: Intel to ship more SOCs than PC CPUs -- someday
  37. ^ Intel to extend ArF lithography to 11 nm
  38. ^ Focus Shifts to Affordability.
  39. ^ 25 nm NAND announcement
  40. ^ C. Bencher, Nanochip Technology Journal, 2007.
  41. ^ U.S. Patent 7808053.
  42. ^ IEDM 2011 Press Tip Sheet

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