X86 instruction listings

X86 instruction listings

The x86 instruction set has undergone numerous changes over time. Most of them were to add new functionality to the instruction set.

x86 integer instructions

This is the full 8086/8088 instruction set, but most, if not all of these instructions are available in 32-bit mode, they just operate on 32-bit registers (eax, ebx, etc) and values instead of their 16-bit (ax, bx, etc) counterparts. See also x86 assembly language for a quick tutorial for this chip.

Original 8086/8088 instructions

Added with 80386

Added with Pentium MMX

RDPMC*

Added with Pentium Pro

Conditional MOV:CMOVA, CMOVAE, CMOVB, CMOVBE, CMOVC, CMOVE, CMOVG, CMOVGE, CMOVL, CMOVLE, CMOVNA, CMOVNAE, CMOVNB, CMOVNBE, CMOVNC, CMOVNE, CMOVNG, CMOVNGE, CMOVNL, CMOVNLE, CMOVNO, CMOVNP, CMOVNS, CMOVNZ, CMOVO, CMOVP, CMOVPE, CMOVPO, CMOVS, CMOVZ, SYSENTER (SYStem call ENTER), SYSEXIT (SYStem call EXIT), RDPMC*, UD2

* RDPMC "was introduced in the Pentium Pro processor and the Pentium processor with MMX technology."

Added with AMD K6-2

SYSCALL, SYSRET (functionally equivalent to SYSENTER and SYSEXIT)


=Added with SSE=

MASKMOVQ, MOVNTPS, MOVNTQ, PREFETCH0, PREFETCH1, PREFETCH2, PREFETCHNTA, SFENCE (for Cacheability and Memory Ordering)

Added with SSE2

CLFLUSH, LFENCE, MASKMOVDQU, MFENCE, MOVNTDQ, MOVNTI, MOVNTPD, PAUSE (for Cacheability)

Added with SSE3

LDDQU (for Video Encoding)

MONITOR, MWAIT (for thread synchronization; only on processors supporting Hyper-threading and some dual-core processors like Core 2, Phenom and others)

Added with Intel VT

VMPTRLD, VMPTRST, VMCLEAR, VMREAD, VMWRITE, VMCALL, VMLAUNCH, VMRESUME, VMXOFF, VMXON

Added with AMD-V

CLGI, SKINIT, STGI, VMLOAD, VMMCALL, VMRUN, VMSAVE (SVM instructions of AMD-V)

Added with x86-64

CMPXCHG16B (CoMPaRe and eXCHanGe 16 bytes), RDTSCP (ReaD Time Stamp Counter P?)

Added with SSE4a

LZCNT, POPCNT (POPulation CouNT) - advanced bit manipulation

x87 floating-point instructions

Original 8087 instructions

F2XM1, FABS, FADD, FADDP, FBLD, FBSTP, FCHS, FCLEX, FCOM, FCOMP, FCOMPP, FDECSTP, FDISI, FDIV, FDIVP,FDIVR, FDIVRP, FENI, FFREE, FIADD, FICOM, FICOMP, FIDIV, FIDIVR, FILD, FIMUL, FINCSTP, FINIT, FIST, FISTP, FISUB, FISUBR, FLD, FLD1, FLDCW, FLDENV, FLDENVW, FLDL2E, FLDL2T, FLDLG2, FLDLN2, FLDPI, FLDZ, FMUL, FMULP, FNCLEX, FNDISI, FNENI, FNINIT, FNOP, FNSAVE, FNSAVEW, FNSTCW, FNSTENV, FNSTENVW, FNSTSW, FPATAN, FPREM, FPTAN, FRNDINT, FRSTOR, FRSTORW, FSAVE, FSAVEW, FSCALE, FSQRT, FST, FSTCW, FSTENV, FSTENVW, FSTP, FSTSW, FSUB, FSUBP, FSUBR, FSUBRP, FTST, FWAIT, FXAM, FXCH, FXTRACT, FYL2X, FYL2XP1

Added in specific processors

Added with 80287

FSETPM

Added with 80387

FCOS, FLDENVD, FNSAVED, FNSTENVD, FPREM1, FRSTORD, FSAVED, FSIN, FSINCOS, FSTENVD, FUCOM, FUCOMP, FUCOMPP

Added with Pentium Pro

* FCMOV variants: FCMOVB, FCMOVBE, FCMOVE, FCMOVNB, FCMOVNBE, FCMOVNE, FCMOVNU, FCMOVU
* FCOMI variants: FCOMI, FCOMIP, FUCOMI, FUCOMIP

Added with SSE

* FXRSTOR*, FXSAVE*

* Also supported on later Pentium IIs, though they do not contain SSE support

Added with SSE3

FISTTP (x87 to integer conversion)

Undocumented instructions

FFREEP performs FFREE ST(i) and pop stack

SIMD instructions


=MMX instructions=

"added with Pentium MMX"EMMS, MOVD, MOVQ, PACKSSDW, PACKSSWB, PACKUSWB, PADDB, PADDD, PADDSB, PADDSW, PADDUSB, PADDUSW, PADDW, PAND, PANDN, PCMPEQB, PCMPEQD, PCMPEQW, PCMPGTB, PCMPGTD, PCMPGTW, PMADDWD, PMULHW, PMULLW, POR, PSLLD, PSLLQ, PSLLW, PSRAD, PSRAW, PSRLD, PSRLQ, PSRLW, PSUBB, PSUBD, PSUBSB, PSUBSW, PSUBUSB, PSUBUSW, PSUBW, PUNPCKHBW, PUNPCKHDQ, PUNPCKHWD, PUNPCKLBW, PUNPCKLDQ, PUNPCKLWD, PXOR


=MMX+ instructions=

added with Athlon

Same as the SSE SIMD Integer Instructions which operated on MMX registers.


=EMMX instructions=

added with 6x86MX from Cyrix, deprecated now

PAVEB, PADDSIW, PMAGW, PDISTIB, PSUBSIW, PMVZB, PMULHRW, PMVNZB, PMVLZB, PMVGEZB, PMULHRIW, PMACHRIW

3DNow! instructions

added with K6-2

FEMMS, PAVGUSB, PF2ID, PFACC, PFADD, PFCMPEQ, PFCMPGE, PFCMPGT, PFMAX, PFMIN, PFMUL, PFRCP, PFRCPIT1, PFRCPIT2, PFRSQIT1, PFRSQRT, PFSUB, PFSUBR, PI2FD, PMULHRW, PREFETCH, PREFETCHW

3DNow!+ instructions

added with Athlon

PF2IW, PFNACC, PFPNACC, PI2FW, PSWAPD

added with Geode GX

PFRSQRTV, PFRCPV


=SSE instructions=

"added with Pentium III""also see integer instruction added with Pentium III"

E SIMD Floating-Point Instructions

ADDPS, ADDSS, CMPPS, CMPSS, COMISS, CVTPI2PS, CVTPS2PI, CVTSI2SS, CVTSS2SI, CVTTPS2PI, CVTTSS2SI, DIVPS, DIVSS, LDMXCSR, MAXPS, MAXSS, MINPS, MINSS, MOVAPS, MOVHLPS, MOVHPS, MOVLHPS, MOVLPS, MOVMSKPS, MOVNTPS, MOVSS, MOVUPS, MULPS, MULSS, RCPPS, RCPSS, RSQRTPS, RSQRTSS, SHUFPS, SQRTPS, SQRTSS, STMXCSR, SUBPS, SUBSS, UCOMISS, UNPCKHPS, UNPCKLPS

E SIMD Integer Instructions

ANDNPS, ANDPS, ORPS, PAVGB, PAVGW, PEXTRW, PINSRW, PMAXSW, PMAXUB, PMINSW, PMINUB, PMOVMSKB, PMULHUW, PSADBW, PSHUFW, XORPS

SSE2 instructions

"added with Pentium 4""also see integer instructions added with Pentium 4"

E2 SIMD Floating-Point Instructions

ADDPD, ADDSD, ANDNPD, ANDPD, CMPPD, CMPSD*, COMISD, CVTDQ2PD, CVTDQ2PS, CVTPD2DQ, CVTPD2PI, CVTPD2PS, CVTPI2PD, CVTPS2DQ, CVTPS2PD, CVTSD2SI, CVTSD2SS, CVTSI2SD, CVTSS2SD, CVTTPD2DQ, CVTTPD2PI, CVTPS2DQ, CVTTSD2SI, DIVPD, DIVSD, MAXPD, MAXSD, MINPD, MINSD, MOVAPD, MOVHPD, MOVLPD, MOVMSKPD, MOVSD*, MOVUPD, MULPD, MULSD, ORPD, SHUFPD, SQRTPD, SQRTSD, SUBPD, SUBSD, UCOMISD, UNPCKHPD, UNPCKLPD, XORPD

* CMPSD "and" MOVSD "have the same name as the string instruction mnemonics" CMPSD (CMPS) "and" MOVSD (MOVS)", however, the former refer to scalar double-precision floating-points whereas the latters refer to doubleword strings."

E2 SIMD Integer Instructions

MOVDQ2Q, MOVDQA, MOVDQU, MOVQ2DQ, PADDQ, PSUBQ, PMULUDQ, PSHUFHW, PSHUFLW, PSHUFD, PSLLDQ, PSRLDQ, PUNPCKHQDQ, PUNPCKLQDQ

SSE3 instructions

"added with Pentium 4 supporting SSE3""also see integer and floating-point instructions added with Pentium 4 SSE3"

E3 SIMD Floating-Point Instructions

*ADDSUBPD, ADDSUBPS (for Complex Arithmetic)
*HADDPD, HADDPS, HSUBPD, HSUBPS (for Graphics)
*MOVDDUP, MOVSHDUP, MOVSLDUP (for Complex Arithmetic)

SSSE3 instructions

"added with Xeon 5100 series and initial Core 2"
*PSIGNW, PSIGND, PSIGNB
*PSHUFB
*PMULHRSW, PMADDUBSW
*PHSUBW, PHSUBSW, PHSUBD
*PHADDW, PHADDSW, PHADDD
*PALIGNR
*PABSW, PABSD, PABSB

SSE4 instructions

SSE4.1

"added with Core 2 x9000 series"
*MPSADBW
*PHMINPOSUW
*PMULLD, PMULDQ
*DPPS, DPPD
*BLENDPS, BLENDPD, BLENDVPS, BLENDVPD, PBLENDVB, PBLENDW
*PMINSB, PMAXSB, PMINUW, PMAXUW, PMINUD, PMAXUD, PMINSD, PMAXSD
*ROUNDPS, ROUNDSS, ROUNDPD, ROUNDSD
*INSERTPS, PINSRB, PINSRD/PINSRQ, EXTRACTPS, PEXTRB, PEXTRW, PEXTRD/PEXTRQ
*PMOVSXBW, PMOVZXBW, PMOVSXBD, PMOVZXBD, PMOVSXBQ, PMOVZXBQ, PMOVSXWD, PMOVZXWD, PMOVSXWQ, PMOVZXWQ, PMOVSXDQ, *PMOVZXDQ
*PTEST
*PCMPEQQ
*PACKUSDW
*MOVNTDQA

SSE4a

"added with Phenom processors"
*EXTRQ/INSERTQ
*MOVNTSD/MOVNTSS

SSE4.2

"to be added with Nehalem processors"
*CRC32
*PCMPESTRI
*PCMPESTRM
*PCMPISTRI
*PCMPISTRM
*PCMPGTQ

Undocumented instructions

The x86 CPUs contain undocumented instructions which are implemented on the chips but never listed in any official available document.

References

External links

* [http://home.comcast.net/~fbui/intel.html The 8086 / 80286 / 80386 / 80486 Instruction Set ]
* [http://www.intel.com/products/processor/manuals/index.htm Free IA-32 and x86-64 documentation] , provided by Intel
* [http://www.linuxmedialabs.com/nasm/html/nasmdoca.html Netwide Assembler x86 Instruction Reference] (from Netwide Assembler)
* [http://siyobik.info/index.php?module=x86 x86 Instruction Set Reference]


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