SSE5

SSE5

The SSE5 (short for Streaming SIMD Extensions version 5), announced by AMD on August 30, 2007, is an extension to the 128-bit SSE core instructions in the AMD64 instruction set for the Bulldozer processor core, due to begin production in 2009.

SSE5 consists of 170 instructions (including 46 base instructions), many of which are designed to improve single-threaded performance. Some SSE5 instructions are 3-operand instructions, the use of which will increase the average number of instructions per cycle achievable by x86 code.cite web | url=http://www.theregister.co.uk/2007/08/30/amd_sse5/ | title=AMD plots single thread boost with x86 extensions | date=August 30 2007 | first=Ashlee | last=Vance | pubisher=The Register] Selected new instructions include: [cite web | url=http://developer.amd.com/SSE5 | title=128-Bit SSE5 Instruction Set | publisher=AMD Developer Central | accessdate=2008-01-28]

* Fused multiply-accumulate (FMACxx) instructions
* Integer multiply-accumulate (IMAC, IMADC) instructions
* Permutation (PPERM, PERMPx) and conditional move (PCMOV) instructions
* Precision control, rounding, and conversion instructions

AMD claims SSE5 will provide dramatic performance improvements, particularly in high-performance computing (HPC), multimedia and computer security applications, including a 5x performance gain for Advanced Encryption Standard (AES) encryption and a 30% performance gain for discrete cosine transform (DCT) used to process video streams.

To avoid confusion it is worth noting that (AMD's) SSE5 does not include all (Intel's) SSE4 instructions. In other words, it is not a superset of SSE4 but a competitor to it. Likewise, Intel's pre-Nehalem cores contain only a partial implementation of SSE4, called SSE4.1. This poses some difficulty and extra work for compilers and assembly-level hand tuning of code.

References

See also

* SSE, SSE2, SSE3, SSSE3, SSE4, AVX
* 3DNow! Professional
* x86 instruction listings
* Fused multiply-add

External links

* [http://developer.amd.com/cpu/SSE5 AMD SSE5 page]
* [http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=3073 A New SSE Instruction Set: AMD Announces SSE5] , AnandTech, August 30, 2007, accessed August 30, 2007.
* [http://www.dailytech.com/article.aspx?newsid=8666 AMD Announces SSE5 Instruction Set] , DailyTech, August 30, 2007, accessed August 30, 2007.


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