Advanced Vector Extensions
- Advanced Vector Extensions
The Intel Advanced Vector Extensions is a set of SIMD instructions announced by Intel at the Spring Intel Developer Forum in April 2008. These instructions will appear on 2010 Intel processors such as Sandy Bridge.
White papers are available at the Intel Software Network site for Intel AVX. [cite web | url=http://softwareprojects.intel.com/avx/ | title=Intel Software Network | publisher=Intel | accessdate=2008-04-05] There is also an online reference manual. [cite web | url=http://softwarecommunity.intel.com/isn/downloads/intelavx/Intel-AVX-Programming-Reference-31943302.pdf | title=Intel Advanced Vector Extensions Programming Reference | publisher=Intel | accessdate=2008-04-05]
Features
General
*Suited for highly FP intensive workloads.
**Multimedia processing.
**3D modeling.
**Scientific simulation.
**Financial analysis.
*Up to 256-bit wide vector FP data.
*3 and 4 operands supported.
*Power efficient, idle power usage is insignificant.
*Up to 2x the FLOPS compared to before, due to the wider vectors supported.
*Performance scales with threads, cores, and interconnects.
*Programming flexibility.
*Improves performance of both existing and new applications that benefit from AVX.
Cryptography
*AES acceleration instructions
*PCLMULQDQ instruction useful for finite field arithmetic in GF(2n) and thus implementation of elliptic curve cryptography.
Instructions
*> 200 legacy Intel SSE instructions are updated to handle flexible memory alignment and distinct source operands.
*< 100 legacy Intel SSE instructions are updated to support 256-bit vectors.
*< 100 new instructions.
*Broadcast, permute, fused multiply-add instructions.
*4 operand instructions include: FMA, generalized shuffles, and blending of variables.
Future
*Built-in future scalability.
*256- and 512-bit vector integers.
*512- and 1024-bit vector FPs.
Future Intel instructions
Intel will introduce hardware FMA (fused multiply-add) in 2011 (or later). [http://pc.watch.impress.co.jp/docs/2008/0407/kaigai434.htm] These instructions may arrive with the 22 nm process, also slated for 2011.
References
ee also
* SSE, SSE2, SSE3, SSSE3, SSE4, SSE5
Wikimedia Foundation.
2010.
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