SGPIO

SGPIO is an acronym for Serial General Purpose Input/Output which is a 4-signal (or 4-wire) bus used between a Host Bus Adapter (HBA) and a backplane. Out of the 4 signals, 3 are driven by the HBA and 1 is driven by the backplane. Typically, the HBA is a storage controller located inside a server, desktop, rack or workstation computer that interfaces with hard disk drives (HDDs) to store and retrieve data.

The SGPIO specification is given the official name SFF-8485 and is maintained by the SFF Committee. For the International Blinking Pattern Interpretation which describes how SGPIO signals is interpreted into blinking LEDs on disk arrays and storage backplanes see the article IBPI.

Host Bus Adapters with SGPIO bus interface

The SGPIO signal consists of 4 electrical signals. It typically originates from a Host Bus Adapter (HBA). The picture shows a typical HBA with two 4x iPass connectors.The iPass connectors carry both SAS/SATA electrical connections between the HBA and the hard drives as well as the 4 SGPIO signals.

Connection from the HBA to Backplane

An iPass Cable is used between the HBA and the backplane. Note that both SATA/SAS signals and SGPIO signals travel in the same cable.

Backplanes with SGPIO bus interface

A backplane is a circuit board with connectors and power circuitry where hard drives can plug in. The backplane can have multiple slots, where each slot can be populated with a hard drive. Typically the backplane is outfitted with LEDs that indicate the status of that slot. The LEDs for each slot and their color indicate a particular state of that slot. Also an LED many emit a particular blink pattern to indicate a particular status for that slot.

SGPIO Interpretation and LED Blinking patterns

Although many hardware vendors define their own proprietary LED blinking pattern, the common standard for SGPIO interpretation and LED blinking pattern can be found in the IBPI specificaiton.

Vendors use typically 2 or 3 LEDs per slot on backplanes. In both implementations a green LED indicates presence and/or activity. For 2 LEDs per slot backplanes the second LED is a "status LED", where as in 3 LED backplanes the second and third LEDs are referred to as "Locate" and "Fail" LEDs.

Electrical Characteristics of the SGPIO bus

The SGPIO bus consists of 4 signals lines and originates at the HBA, referred to as the 'initiator'. The SGPIO bus ends on a backplane referred to as the target. If a backplane does not exist, the HBA may still drive the bus without any harm caused to the system. If a backplane (or target) does exist, it can communicate back to the HBA using the 4th wire.

The SGPIO bus is an open collector bus with 2.0kΏ pull-up resistors located at the HBA and the backplane. As on any open collector bus, information is transferred by devices on the bus pulling the lines to ground (GND) using an open collector transistor or open drain FET.

Signal lines of the SGPIO bus

SClock

The SGPIO bus has a dedicated clock line, driven by the initiator. The maximum clock rate is 100kHz, although many implementations use clock rates that are slower (typ 48 kHz).

SLoad

This line is synchronous to the clock, and is used to indicate the start of a new frame of data.A new frame in SGPIO is indicated by the SLoad being high at a rising edge of a clock after having been low for at least 5 clock cycles. The following 4 falling clock edges after a start condition is used to carry a 4-bit value from the HBA to the backplane. The definition of this value is proprietary and is defined between system vendors.

SDataOut

This line carries 3 bits of data from the HBA to the backplane, where the first bit typically carries 'activity', second bit carries 'locate' and the third bit carries 'fail'. A low value for the first bit indicates 'not activity' or inactive, and high indicates activity.

SDataIn

This line is used by the backplane and indicates some condition on the backplane back to the HBA. The first bit being high commonly indicates the presence of a drive. The two following bits are typically unused, and driven low. Because this line would be high for all 3 bits when no backplane is connected, an HBA can detect the presence of a backplane by the second or third bit of the SDataIn being driven low.

The SDataIn and SdataOut then repeats with 3 clocks per drive until the last drive is reached, and the cycle starts over again.

SGPIO Implementation

There are varieties in how the SGPIO bus is implemented between vendors of HBAs and storage controllers. Some vendors will send a continuous stream of data, which is advantageous to quickly update the LEDs on a backplane after a cables are removed and re-inserted. Other vendors send data only when there is a need to update the LED pattern.

Adoption of the SGPIO Specification

SGPIO and the SGPIO spec is generally adopted and implemented in products from most major HBA and Storage Controller vendors such as LSI, Intel, Adaptec, Nvidia, Broadcom, Marvell Technology Group and PMC-Sierra.Most products shipping with support for SAS and SATA drives support this standard.

SGPIO Timeout Conditions

The SGPIO spec calls for the target to turn off all indicators when SClock, SLoad and SDataOut has been high for 64ms. In practice this is not consistently followed by all vendors. Also, in implementation by some vendors the clock may be halted sporadically or stopped during or between cycles. Another impractical variation between vendors is how the clock is left after a cycle.

Backplane Implementations of the SGPIO bus

The idea behind this specification was to be able to use low cost CPLDs or microcontrollers on a backplane to drive LEDs. In practice, it has been found that there are variations in timing and interpretations of the bits between vendors, thus a simple CPLD would only work for a specific implementation thoroughly tested with one product from one vendor. A microcontroller is more applicable for this purpose, although the 4-bit SGPIO interface is a custom bus not found on micros. Also, sampling of the 4-bit lines using GPIOs 100 kHz bit operations is too slow for many low-cost micros to handle, while simultaneously handling LED and other functions. The length of the bit stream varies between HBA or storage controller. Some vendors will stop the bit-stream when reaching the desired drive, other will clock it all the way through. For some SAS-expanders the bit streams may be as long as 36x3=108 bits.

The safest implementation which ensures compatibility between all HBA and storage controller vendors is to use an ASIC, specifically a combination of a micro controller core with a hardware SGPIO interface. This concept was patented in 2006 by AMI and implemented in a series of backplane controller chips named the MG9071, MG9072, MG9077, and MG9082.

These chips will receive 1 or 2 SGPIO streams and drive LEDs accordingly. The latest chip from AMI, the MG9077, can be configured by pull-up and pull-down resistors to adopt to 16 different configurations of SGPIO buses and drive LEDs accordingly. Since the availability of these chips from AMI, major OEMs like NEC, Hitachi, Supermicro, IBM, Sun Microsystems, and others are using these chips on their backplanes to receive the SGPIO streams from a variety of HBA vendors and on-board controller chips, and consistently drive LEDs with a pre-determined blinking pattern.

External links

* [ftp://ftp.seagate.com/sff/SFF-8485.PDF SFF-8485] SGPIO specification
* [ftp://ftp.seagate.com/sff/ SFF Documents] (Documents & Specifications)
* [http://www.ami.com/products/catpage.cfm?CatID=14 Backplane Controllers from AMI]

*MG9077 Backplane Management Controller With Dual SGPIO
*MG9082 Backplane Management Controller With Dual SGPIO and IBPI support