# Offset binary

Offset binary

Offset binary, also referred to as excess-K, is a digital coding scheme where all-zero corresponds to the minimal negative value and all-one to the maximal positive value. There is no standard for offset binary, but most often the offset K for an n-bit binary word is K=2^(n-1). This has the consequence that the "zero" value is represented by a 1 in the most significant bit and zero in all other bits, and in general the effect is conveniently the same as using two's complement except that the most significant bit is inverted. It also has the consequence that in a logical comparison operation, one gets the same result as with a twos' complement numerical comparison operation, whereas, in twos' complement notation a logical comparison will agree with twos' complement numerical comparison operation if and only if the numbers being compared have the same sign. Otherwise the sense of the comparison will be inverted, with all negative values being taken as being larger than all positive values.

One historically prominent example of offset-64 ("excess 64") notation was in the floating point (exponential) notation in the IBM System/360 and System/370 generations of computers. The "characteristic" (exponent) took the form of an seven-bit excess-64 number (The high-order bit of the same byte contained the sign of the significand). The IEEE Standard for Floating-Point Arithmetic (IEEE 754) uses various sizes of exponent, but also uses offset notation for the format of each precision. Unusually however, instead of using "excess 2^(n-1)" it uses "excess 2^(n-1)-1" which means that inverting the leading (high-order) bit of the exponent will not convert the exponent to correct twos' complement notation.

Offset binary is often used in digital signal processing (DSP). Most analog to digital (A/D) and digital to analog (D/A) chips are unipolar, which means that they cannot handle bipolar signals (signals with both positive and negative values). A simple solution to this is to bias the analog signals with a DC offset equal to half of the A/D and D/A converter's range. The resulting digital data then ends up being in offset binary format.

Most standard computer CPU chips cannot handle the offset binary format directly. CPU chips typically can only handle signed and unsigned integers, and floating point value formats. Offset binary values can be handled in several ways by these CPU chips. The data may just be treated as unsigned integers, requiring the programmer to deal with the zero offset in software. The data may also be converted to signed integer format (which the CPU can handle natively) by simply subtracting the zero offset. Notice that as a consequence of the fact that the commonest offset for an n-bit word is 2^(n-1), which implies that the first bit is inverted relative to twos' complement, one need not have a separate subtraction step, but simply can invert the first bit. This sometimes is a useful simplification in hardware, and can be convenient in software as well.

Offset binary occurs so frequently in digital signal processing that many DSP chips can handle offset binary without requiring any data conversion.

Table of offset binary for 4 bits, with twos' complement for comparison

Offset Binary code, K=8 Decimal code Twos' complement Binary
1111 7 0111
1110 6 0110
1101 5 0101
1100 4 0100
1011 3 0011
1010 2 0010
1001 1 0001
1000 0 0000
0111 −1 1111
0110 −2 1110
0101 −3 1101
0100 −4 1100
0011 −5 1011
0010 −6 1010
0001 −7 1001
0000 −8 1000

Offset binary may be converted into two's complement by inverting the most significant bit. For example, with 8 bit values, the offset binary value may be XOR'ed with 0x80 in order to convert to two's complement. In specialised hardware it may be simpler to accept the bit as it stands, but to apply its value in inverted significance.

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