TILE64

Infobox Computer Hardware Cpu
name = TILE64


image_size =
caption =
produced-start = 2007
produced-end =
slowest = 600
fastest = 900
slow-unit = MHz
fast-unit = MHz
fsb-slowest =
fsb-fastest =
fsb-slow-unit =
fsb-fast-unit =
size-from = 0.045
size-to = 0.09
manuf1 = Tilera
core1 =
sock1 =
arch =
microarch =
numcores = 64

TILE64 is a microcontroller manufactured by Tilera. It consists of a mesh network of 64 "tiles", where each tile houses a general purpose processor, cache, and a non-blocking router, which the tile uses to communicate with the other tiles on the processor.

The short-pipeline, in-order, three-issue cores implement a MIPS-derived VLIW instruction set. Each core has a register file and three functional units: two integer arithmetic logic units and a load-store unit. Each of the cores ("tile") has its own L1 and L2 caches and a L3 cache that is considered an aggregate of all the L2 caches. [cite news |title=Massively multicore processor runs Linux |url=http://www.linuxdevices.com/news/NS8981295285.html |publisher=linuxdevices.com |first=Henry |last=Kingman |date=August 20, 2007 ] A core is able to run a full operating system on its own or multiple cores can be used to run a symmetrical multi-processing operating system.

TILE64 has four DDR2 controllers, two 10-gigabit Ethernet interfaces, two four-lane PCIe interfaces, and a "flexible" input/output interface, which can be software-configured to handle a number of protocols. The processor is fabricated using a 90 nm process and runs at speeds of 600 to 900 MHz.

According to CTO and co-founder Anant Agarwal, Tilera will target the chip at networking equipment and digital video markets where the demands for computing processing are high. [cite news |first=Mark |last=Boslet |title=Start-up Tilera to Unveil 64-core chip |url=http://origin.mercurynews.com/businessheadlines/ci_6668379 |publisher=San Jose Mercury News |date=August 20, 2007 ]

References

External links

* [http://www.tilera.com/products/processors.php Tilera Website]
*http://arstechnica.com/articles/paedia/cpu/MIT-startup-raises-multicore-bar-with-new-64-core-CPU.ars
*http://news.com.com/Chipmakers+aim+to+unclog+data+paths/2100-1006_3-6203218.html