DEC PRISM

Not to be confused with Apollo PRISM.

PRISM was a 32-bit RISC instruction set architecture (ISA) developed by Digital Equipment Corporation (DEC). It was the final outcome of a number of DEC research projects from the 1982–1985 time-frame, and was at the point of delivering silicon in 1988 when the management canceled the project. The next year work on the Alpha started, based heavily on the PRISM design.

Background

In the early 1980s DEC was a huge success, flush with cash and infused with a feeling of invincibility. Projects were started all over the company to chase the "next big thing", with little or no overall direction or managerial oversight. RISC computing was one of those next big things, and in the period from 1982 to 1985 no less than four attempts were made to create a RISC chip at different divisions.

Titan from DEC's Western Research Laboratory (WRL) in Palo Alto, California was a high-performance ECL based design that started in 1982, intended to run Unix. SAFE (Streamlined Architecture for Fast Execution) was a 64-bit design that started the same year, designed by Alan Kotok (of Spacewar! fame) and Dave Orbits and intended to run VMS. HR-32 (Hudson, RISC, 32-bit) started in 1984 by Rich Witek and Dan Dobberpuhl at the Hudson fab, intended to be used as a co-processor in VAX machine. The same year Dave Cutler started the CASCADE project at DECwest in Bellevue, Washington.

PRISM

Eventually Cutler was asked to define a single RISC project in 1985, selecting Rich Witek as the chief architect. The design started as a 64-bit chip, but was later "downsized" to 32-bits. In August 1985 the first draft of a high-level design was delivered, and work began on the detailed design. The PRISM specification was developed over a period of many months by a five person team: Dave Cutler, Dave Orbits, Rich Witek, Dileep Bhandarkar, and Wayne Cardoza. This work was 98% done 1985-1986 and was heavily supported by simulations by Pete Benoit on a large VAXcluster.

In terms of integer operations, the PRISM architecture was similar to the MIPS designs. Of the 32-bit instructions, the 6 highest and 5 lowest bits were the instruction, leaving the rest of the word for encoding either a constant or register locations. Sixty-four 32-bit registers were included, as opposed to thirty-two in the MIPS, but usage was otherwise similar. The PRISM and MIPS also lack the register windows that were a hallmark of the "other" design, Berkeley RISC/SPARC.

The PRISM design was notable for several aspects of its instruction set, however. Notably, PRISM included Epicode (extended processor instruction code), which defined a number of "special" instructions intended to offer the operating system a stable ABI across multiple implementations. Epicode was given its own set of 22 32-bit registers to use. A set of vector processing instructions were later added as well, supported by an additional sixteen 64-bit vector registers that could be used in a variety of ways.

Two versions of the system were planned, DECwest worked on a "high-end" ECL implementation known as Crystal, while the Semiconductor Advanced Development team worked on MicroPRISM, a CMOS version. MicroPRISM was finished first and was sent for test fabrication in April 1988. Additionally, Cutler led development on a new microkernel-based operating system code-named Mica, which was to offer Unix-like and VMS-like "personalities" on top of a common substrate of services.

Friction and cancellation

Throughout the PRISM period, DEC was involved in a major debate over the future direction of the company. As newer workstations were introduced, the performance benefit of the VAX was constantly eroded, and the price/performance ratio completely undermined. Different groups within the company debated how to best respond. Some advocated moving the VAX into the "high-end", abandoning the low-end to the workstations. Others suggested moving into the workstation market using a commodity processor. Still others suggested re-implementing the VAX on a RISC processor.

This led to considerable problems with turf wars between the various groups. Competition between the divisions delayed the architecture review, which wasn't closed until 1986. Work on associated support chips, the memory management unit and floating point unit, were later interrupted by yet another debate on whether or not the design should be 32- or 64-bit. The MicroPRISM design was not finalized until April 1988.

Frustrated with the growing number of losses to cheaper faster competitive machines, independently, a small group outside of Central Engineering, focused on workstations and UNIX/Ultrix, entertained the idea of using an off-the-shelf RISC processor to build a new family of workstations. The group carried out due diligence, eventually choosing the MIPS R2000 as the desired foundation. This group acquired a development machine and, in cooperation with hand-picked members of the Ultrix Engineering Group, prototyped a port of Ultrix to the MIPS R2000 system. From the initial meetings with MIPS to a prototype machine took only 90 days, with full production able to start by January 1989, resulting in the DECstation 3100 and family. At a meeting reviewing the various projects in July 1988, the company decided to cancel PRISM, and continue with the MIPS workstations and high-end VAX products.

Ironically, every attempt to produce a faster VAX that could compete with newer workstations was essentially a failure. The VAX 9000 ran into delays, and by the time it shipped newer Unix workstations had already surpassed it in performance, at a tiny fraction of the cost (or size). Apparently aware of this danger, at the very same meeting where PRISM was canceled, Ken Olsen started a new project to continue exploring a RISC-based VAX. This indirectly led to the formation of the Alpha project the next year.

References

• E-mail with Bob Supnik
• MicroPrism
• Prism documents at bitsavers.org

Further reading

• Bhandarkar, Dileep P. (1995). Alpha Architecture and Implementations. Digital Press.
• Bhandarkar, D. et al. (1990. "High performance issue orientated architecture". Proceedings of Compcon Spring '90, pp. 153–160.
• Conrad, R. et al. (1989). "A 50 MIPS (peak) 32/64 b microprocessor". ISSCC Digest of Technical Papers, pp. 76–77.