- Low-power electronics
Low-power electronics means that the "consumption" of
electric poweris deliberately low, e.g. notebook processors.
The density and speed of integrated circuit computing elements has increased roughly exponentially for a period of several decades, following a trend described by
Moore's Law. While it is generally accepted that this exponential improvement trend will end, it is unclear exactly how dense and fast integrated circuits will get by the time this point is reached. Working devices have been demonstrated that were fabricated with a MOSFET transistorchannel length of 6.3 nanometres using conventional semiconductor materials, and devices have been built that used carbon nanotubes as MOSFET gates, giving a channel length of approximately one nanometre.
The density and computing power of integrated circuits are limited primarily by power dissipation concerns.
An integrated circuit chip contains many capacitive loads, formed both intentionally (as is the case with gate to channel capacitance) and unintentionally (between any conductors that are near each other but not electrically connected). Changing the state of the circuit causes a change in the voltage across these parasitic capacitances, which involves a change in the amount of stored energy. As the capacitive loads are charged and discharged through resistive devices, an amount of energy comparable to that stored in the capacitor is dissipated as heat.
The result of heat dissipation on state change is to limit the amount of computation that may be performed on a given power budget. While device shrinkage can reduce some of the parasitic capacitances, the number of devices on an integrated circuit chip has increased more than enough to compensate for reduced capacitance in each individual device.
Some circuits -- dynamic logic -- require some minimum clock rate in order to function properly, wasting "dynamic power" even when it has nothing to do.Other circuits -- most famously, the
RCA 1802, but also many later chips such as the WDC 65C02, the 80C85, the Freescale 68HC11, and some other CMOSchips -- use "fully static logic" that have no minimum clock rate, but can "stop the clock" and hold their state indefinitely.When the clock is stopped, such circuits use no "dynamic power", but they still have a small static power consumption caused by "leakage current".
As circuits shrink,
Subthreshold leakagecurrent is becoming much more important. This leakage current results in power consumption even when no switching is taking place (static power consumption), and with modern chips this current is frequently more than 50% of power used by the IC. This loss can be reduced by raising the threshold voltageand lowering the supply voltage. Both of these changes slow the circuit down significantly, and so some modern low-power circuits use dual supply voltages to provide speed on critical parts of the circuit, and lower power on non-critical paths. Some circuits even use different transistors (with different threshold voltages) in different parts of the circuit in an attempt to further reduce power consumption without significant performance loss.
Another method used to reduce static power consumption is the use of sleep transistors to disable entire blocks when not in use. By shutting down a leaky functional block until it is used, leakage current can be reduced significantly. For some embedded systems that only function for short periods at a time, this can dramatically reduce power consumption. Since systems that are dormant for long periods of time and "wake up" to perform a periodic activity are often in isolated locations monitoring some sort of activity, they are generally battery or solar powered and power consumption is a key design factor.
Two other approaches exist to lowering the power cost of state changes. One is to reduce the operating voltage of the circuit, or to reduce the voltage change involved in a state change (making a state change only change node voltage by a fraction of the supply voltage —
Low voltage differential signaling). This approach is limited by thermal noise within the circuit. There is a characteristic voltage proportional to the device temperature and to the Boltzmann constant, which the state switching voltage must exceed in order for the circuit to be resistant to noise. This is typically on the order of 50–100 mV, for devices rated to 100 degrees Celsius external temperature (about 4 "kT", where "T" is the device's "internal" temperature in kelvins and "k" is the Boltzmann constant).
The second approach is to attempt to provide charge to the capacitive loads through paths that are not predominantly resistive. This is the principle behind
adiabatic circuits. The charge is supplied either from a variable-voltage inductive power supply, or by other elements in a reversible logic circuit. In both cases, the charge transfer must be primarily regulated by the non-resistive load. As a practical rule of thumb, this means the rate of change of a signal must be much slower than that dictated by the RC time constantof the circuit being driven. In other words, the price of reduced power consumption per unit computation is reduced absolute speed of computation.
In practice, while adiabatic circuits have been built, it has proven very difficult to use it to reduce computation power substantially in practical circuits.
Lastly, there are several techniques used to reduce the number of state changes associated with any given computation. For clocked logic circuits, the technique of
clock gatingis used, to avoid changing the state of functional blocks that aren't required for a given operation. As a more extreme alternative, the asynchronous logicapproach implements circuits in such a way that an explicit externally supplied clock is not required. While both of these techniques are used to varying extents in integrated circuit design, the limit to practical applicability of each appears to have been reached.
If current trends continue, "Energy costs, now about 10% of the average IT budget, could rise to 50% ... by 2010" ( [http://www.businessweek.com/technology/content/may2007/tc20070514_003603.htm "Averting the IT Energy Crunch"] by Rachael King).
The weight and cost of power supply and cooling systems generally depends on the maximum possible power used at some instant.Most desktop computers design power and cooling systems around the worst-case
CPU power dissipationat the maximum frequency, maximum workload, and worst-case environment.To reduce weight and cost, many laptop computers systems choose to use a much lighter, lower-cost cooling system designed around a much lower Thermal Design Power, that is somewhat above expected maximum frequency, typical workload, and typical environment.Typically such systems reduce (throttle) the clock rate when the CPU die temperature gets too hot, reducing the power dissipated to a level that the cooling system can handle.
*Acorn RISC Machine
CPU power dissipation
Cool Chips (symposium)
Common Power Format
Performance per watt
Dynamic frequency scaling
Dynamic voltage scaling
* [http://enws155.eas.asu.edu:8001/confpapers/russ.ps "High-level design synthesis of a low power, VLIW processor for the IS-54 VSELP Speech Encoder"] by Russell Henning and Chaitali Chakrabarti (implies that, in general, if you know exactly what algorithm you want to run, hardware designed to specifically to run that algorithm will use less power than general-purpose hardware running that algorithm at the same speed).
* [http://www.hipeac.net/node/108 CRISP: A Scalable VLIW Processor for Low Power Multimedia Systems] by Francisco Barat 2005
* [http://www.siliconintelligence.com/people/binu/pubs/loopaccel.pdf A Loop Accelerator for Low Power Embedded VLIW Processors] by Binu Mathew and Al Davis
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