Coreboot

Infobox Software
name = Coreboot



caption = Coreboot
author = Ronald G. Minnich, Eric Biederman, Olli Lo, Stefan Reinauer, the coreboot community
developer =
released = 1999
latest release version =
latest release date =
latest preview version =
latest preview date =
platform = x86, PPC
genre = Firmware (BIOS)
license = GNU General Public License
website = [http://coreboot.org/ coreboot.org]

Coreboot (formerly known as LinuxBIOS [cite web
url=http://coreboot.org/pipermail/coreboot/2008-January/029133.html
title= [LinuxBIOS] Welcome to coreboot
date=2008-01-12] ) is a free software project, endorsed by the Free Software Foundation, [ [http://www.fsf.org/campaigns/free-bios.html The Free Software Foundation's Campaign for Free BIOS] ] aimed at replacing the standard BIOS firmware found in most computers with a lightweight firmware system designed to perform only the minimum of tasks necessary to load and run a modern 32-bit or 64-bit operating system.

The coreboot project was started in the winter of 1999 in the Advanced Computing Laboratory at Los Alamos National Laboratory. [coreboot FAQ: [http://www.coreboot.org/FAQ#Who_is_working_on_coreboot.3F Who is working on coreboot?] ] It is licensed under the terms of the GNU General Public License. Main contributors have been LANL, AMD, coresystems GmbH and Linux Networx, Inc, as well as motherboard vendors MSI, Gigabyte and Tyan, by offering coreboot next to their standard BIOS or providing specifications of the hardware interfaces for some of their recent motherboards. However, Tyan seems to have dropped support of coreboot.Fact|date=January 2008

Coreboot support also exists for the AMD Geode. Started as Geode GX support developed by AMD for the OLPC, Artec Group then added Geode LX support for its model DBE61 ThinCan. Recently, that code was adopted by AMD and further polished for the OLPC after it upgraded to the Geode LX platform. That code is now being further developed by the coreboot community to support other Geode-based products.

Google partly sponsors the coreboot project. [ [http://google-code-updates.blogspot.com/2006/11/google-sponsors-linuxbios-project.html Google Sponsors the LinuxBIOS project] ]

Coreboot can be flashed into motherboard using Flashrom.

Design

Coreboot usually loads a Linux kernel, but it can load any other stand-alone ELF executable, such as Etherboot which can boot Linux from a boot server or ADLO [ [http://www.coreboot.org/ADLO coreboot Add-on Layer (ADLO)] ] which loads Microsoft Windows 2000/XP and OpenBSD [ [http://www.missl.cs.umd.edu/sebos_phase2.html SEBOS, Security Enhanced Bootloader for Operating Systems, Phase 2 ] , adding PC BIOS Services to coreboot via Bochs Bios (Link noted to be defunct on 18 July 2008. See [http://web.archive.org/web/20070619101948/www.missl.cs.umd.edu/sebos_phase2.html SEBOS page archived on archive.org] Archived copy of SEBOS Phase 2)] . Coreboot can also load almost any operating system from any supported device, such as Myrinet, Quadrics, or SCI cluster interconnects. Some OSes require legacy BIOS functions (such as Windows 2000/XP/Vista) which are provided by ADLO. Windows Vista additionally depends on specific subsets of ACPI which are not implemented completely yet.

Coreboot does whatever hardware initialization Linux doesn't do and lets Linux finish the hardware initialization.

A unique feature of coreboot is that the x86 version runs in 32-bit mode after executing only ten instructions [ [http://lxr.linux.no/coreboot-v3+r777/arch/x86/geodelx/stage0.S Coreboot v3 early startup code] ] (almost all other x86 BIOSes run exclusively in 16-bit mode).

Coreboot can boot other kernels, or pass control to a boot loader to boot a kernel/image instead. It can also boot a Plan 9 from Bell Labs kernel directly. A coreboot capable version of GNU GRUB 2 is still in development.

By default, Coreboot does not provide BIOS call services. An add-on called ADLO can be used to provide BIOS calls and thus allow Coreboot to load OS's that require those services. Most modern operating systems, however, access hardware in another manner and only use BIOS calls as a fallback mechanism.

Developing and debugging coreboot

Since Coreboot must initialize the bare hardware, it must be ported to every chipset and motherboard that it supports. Before initializing RAM, Coreboot initializes the serial port (addressing Cache and Registers only), so it can send out debug text to a connected terminal. It can also send byte codes to port 0x80 that are displayed on a two-hex-digit display of a connected POST card. Another porting aid is the commercial "RD1 BIOS Savior" product from [http://www.ioss.com.tw/ IOSS] , which is a combination of two boot memory devices that plugs into the boot memory socket and has a manual switch to select between the two devices. The computer can boot from one device, and then the switch can be toggled to allow the computer to reprogram or "flash" the second device. A more expensive alternative is an external EPROM/flash programmer. There are also CPU emulators that either replace the CPU or connect via a JTAG port. Code can be built on, or downloaded to, BIOS emulators rather than flashing the BIOS device.

Initializing DRAM

The most difficult hardware that coreboot initializes is the DRAM controllers and DRAM. In some cases, technical documentation how to do this is NDA protected or unavailable—rendering it impossible to build a coreboot. RAM initialization is particularly difficult because until the RAM is initialized, there is no RAM available for use. Therefore, to initialize DRAM controllers and DRAM without RAM, the initialization code must restrict itself to using only the CPU's general purpose registers for temporary storage. To make this hard task easy, a C compiler that uses registers instead of RAM, called romcc, was built. Using romcc, it is relatively easy to make SMBus accesses to the SPD ROMs of the DRAM DIMMs, that allows the RAM to be used.With newer x86 processors, the processor cache can be used as RAM until DRAM is initialized. The processor cache has to be initialized into Cache-as-RAM mode as well, but this needs fewer instructions than initializing DRAM. Also, the instructions to enable Cache-as-RAM mode are CPU architecture specific, thus more generic than DRAM initialization, which is chipset and mainboard specific.

See also

* OpenBIOS
* Open Firmware
* ThinCan
* Splashtop

References

External links

* [http://www.coreboot.org/ The coreboot Home Page]
* " [http://www-128.ibm.com/developerworks/linux/library/l-bios.html?ca=drs- Open BIOSes for Linux] ", by Peter Seebach
* " [http://www.linux.com/article.pl?sid=06/11/30/199208 LinuxBIOS ready to go mainstream] ", by Bruce Byfield
* " [http://lkml.org/lkml/2007/2/21/490 First desktop motherboard supported by LinuxBIOS: GIGABYTE M57SLI-S4] ", by Brandon Howard
* [http://ftp.belnet.be/mirrors/FOSDEM/2007/FOSDEM2007-LinuxBios.ogg Video recording of Ron Minnich's LinuxBIOS talk from FOSDEM 2007]
* [http://youtube.com/watch?v=nuzRsXKm_NQ Coreboot with X Server Inside (YouTube Video)]
* [http://youtube.com/watch?v=Ig8vW5ACP-k OLPC booting with coreboot (YouTube Video)]