Joint Test Action Group

Joint Test Action Group

Joint Test Action Group (JTAG) is the usual name used for the IEEE 1149.1 standard entitled Standard Test Access Port and Boundary-Scan Architecture for test access ports used for testing printed circuit boards using boundary scan.

JTAG was an industry group formed in 1985 to develop a method to test populated circuit boards after manufacture. At the time, multi-layer boards and non-lead-frame ICs were becoming standard and making connections between ICs not available to probes. The majority of manufacturing and field faults in circuit boards were due to solder joints on the boards, imperfections in board connections, or the bonds and bond wires from IC pads to pin lead frames. JTAG was meant to provide a pins-out view from one IC pad to another so all these faults could be discovered. The industry standard finally became an IEEE standard in 1990 as IEEE Std. 1149.1-1990 after many years of initial use. That same year Intel released the first processor with JTAG: the 80486 which led to quicker industry adoption by all manufacturers. In 1994, a supplement that contains a description of the boundary scan description language (BSDL) was added. Since then, this standard has been adopted by electronics companies all over the world. Boundary-scan is nowadays mostly synonymous with JTAG.

While designed for printed circuit boards, JTAG is nowadays primarily used for accessing sub-blocks of integrated circuits, and is also useful as a mechanism for debugging embedded systems, providing a convenient "back door" into the system. When used as a debugging tool, an in-circuit emulator - which in turn uses JTAG as the transport mechanism - enables a programmer to access an on-chip debug module which is integrated into the CPU, via the JTAG interface. The debug module enables the programmer to debug the software of an embedded system.

Besides debugging, the second purpose of the JTAG interface is allowing device programmer hardware to transfer data into internal non-volatile device memory. Some device programmers serve a double purpose for programming as well as debugging the device.

In most ICs today, all internal registers are on one of many scan chains. This allows all combinational logic to be tested completely even while an IC is in the circuit card and possibly while in a functioning system. When combined with built-in self-test (BIST), the JTAG scan chain enables a low overhead, completely embedded solution to testing an IC for certain static faults (shorts, opens, and logic errors). The scan chain mechanism does not generally help diagnose or test for timing, temperature or other dynamic operational errors that may occur.

Electrical characteristics

A JTAG interface is a special four/five-pin interface added to a chip, designed so that multiple chips on a board can have their JTAG lines daisy-chained together if specific conditions are met [ [http://www.jtagtest.com/faq/jtag-ieee-1149-1/under-what-conditions-can-i-daisy-chain-jtag FAQ: Under what conditions can I daisy-chain JTAG?] ] , and a test probe need only connect to a single "JTAG port" to have access to all chips on a circuit board. The connector pins are
#TDI (Test Data In)
#TDO (Test Data Out)
#TCK (Test Clock)
#TMS (Test Mode Select)
#TRST (Test Reset) optional.Test reset signal is not shown in the image.

Since only one data line is available, the protocol is necessarily serial like SPI. The clock input is at the TCK pin. Configuration is performed by manipulating a state machine one bit at a time through a TMS pin. One bit of data is transferred in and out per TCK clock pulse at the TDI and TDO pins, respectively. Different instruction modes can be loaded to read the chip ID, sample input pins, drive (or float) output pins, manipulate chip functions, or bypass (pipe TDI to TDO to logically shorten chains of multiple chips). The operating frequency of TCK varies depending on the chip, but it is typically 10-100 MHz (100-10 ns per bit).

When performing boundary scan on integrated circuits, the signals manipulated are between different functional blocks of the chip, rather than between different chips.

The TRST pin is an optional active-low reset to the test logic - usually asynchronous, but sometimes synchronous, depending on the chip. If the pin is not available, the test logic can be reset by clocking in a reset instruction synchronously.

Data presented to TDI must be valid for some chip-specific "Setup" time before and "Hold" time after the rising edge of TCK. TDO data is valid for some chip-specific time after the falling edge of TCK. This can be seen e.g. with the JTAG timing diagram of the DS4550 chip (http://pdfserv.maxim-ic.com/en/ds/DS4550.pdf).

Even though few consumer products provide an explicit JTAG port connector, the connections are very often available on the printed circuit board as a remnant from development prototyping. When exploited, these connections often provide an excellent means for reverse engineering.

Test pins

Devices communicate to the world via a set of input and output pins. By themselves, these pins provide limited visibility into the workings of the device. However, devices that support boundary scan contain a shift-register cell for each signal pin of the device. These registers are connected in a dedicated path around the device's boundary (hence the name). The path creates a virtual access capability that circumvents the normal inputs and provides direct control of the device and detailed visibility at its outputs.cite news
first = Rob
last = Oshana
url = http://www.embedded.com/story/OEG20021028S0049
title = Introduction to JTAG
work = Embedded Systems Design
date = October 29, 2002
accessdate = 2007-04-05
]

During testing, I/O signals enter and leave the chip through the boundary-scan cells. The boundary-scan cells can be configured to support external testing for interconnection between chips or internal testing for logic within the chip.

To provide the boundary scan capability, IC vendors add additional logic to each of their devices, including scan registers for each of the signal pins, a dedicated scan path connecting these registers, four or five additional pins, and control circuitry. The overhead for this additional logic is minimal and generally well worth the price to have efficient testing at the board level.

Common extensions

Manufacturer's extensions: Infineon, MIPS EJTAG, Freescale COP, ARM ETM (Embedded Trace Macrocell), OnCE etc.

Widespread uses

*A large proportion of high end embedded systems have a JTAG port Fact|date=February 2007.
*The PCI bus connector standard contains optional JTAG signals on pins 1-5 [ [http://www.techfest.com/hardware/bus/pci.htm#4.10 PCI Local Bus Technical Summary, 4.10 JTAG/Boundary Scan Pins] ] ; PCI-Express contains JTAG signals on pins 5-9 [ [http://www.interfacebus.com/Design_PCI_Express_16x_PinOut.html PCI-Express 16x Connector Pin Out] ] . A special JTAG card can be used to reflash a corrupt BIOS.
*Almost all FPGAs and CPLDs used today can be programmed via the JTAG port.

Client Support

The target's JTAG interface is accessed using some JTAG-enabled application and some JTAG adapter hardware. There is a wide range of such hardware, optimized for purposes such as production testing, debugging high speed systems, low cost microcontroller development, and so on. In the same way, the software used to drive such hardware can be quite varied. Software developers mostly use JTAG for debugging and updating firmware.

JTAG Adapter Hardware

There are no official standards for JTAG adapter physical connectors, but most manufacturers use standard 2.54mm pin header.

Most common JTAG pinouts are [ [http://www.jtagtest.com/pinouts/ JTAG Pinouts] ] :

* ARM 2x7 or 2x10 pin, used by almost all ARM based systems
* MIPS EJTAG (2x7 pin) used for MIPS based systems
* 2x5 pin Altera ByteBlaster-compatible JTAG used by many vendors (i.e. Atmel's AVR 8-bit and 32-bit processors)
* 8pin (single row) generic PLD JTAG compatible with many Lattice ispDOWNLOAD cables

Higher end products frequently use dense connectors to support high-speed tracing in conjunction with JTAG operations. A recent trend is to have development boards integrate a USB interface to JTAG. Production boards often rely on bed-of-nails connections for testing and programming.

If you want to acquire a JTAG adapter, you first need to decide what systems it must support. Everything else follows from that, including your software options. Low-end adapters may cost less than $US 50 and have limited hardware and software support. High-end adapters can cost a hundred times as much, including software support, and have corresponding improvements in capability.

JTAG Software

Open Source

* The [http://www.urjtag.org/ UrJTAG] project supports many JTAG tools, processors, and boards.
* The [http://openocd.berlios.de/web/ OpenOCD] project supports various inexpensive JTAG adapters including USB ones based on FT2232 chips, and is mostly used with ARM projects. It provides GDB and telnet interfaces, both from Linux and from MS-Windows.

Freeware

Because it is so important for developing modern embedded systems software, many chip vendors make a point of providing at least low-end JTAG software at no cost. Some examples include:
* Atmel provides [http://www.atmel.com/products/avrstudio AVR Studio] on MS-Windows, for AVR8 microcontrollers, and a cross-platform AVR32studio product to support AVR32 systems.
* Xilinx provides lower end FPGA development tools at no cost

See also

*Boundary scan test
*Boundary scan description language
* AOI Automated optical inspection
* AXI Automated x-ray inspection
* ICT In-circuit test
* Functional testing (see Acceptance testing)
* Nexus 5001

References

External links

* [http://www.boundary-scan.co.uk/ JTAG/Boundary-scan explained] Knowledge base plus industry links
* [http://web.archive.org/web/20060429074428/http://focus.ti.com/lit/an/ssya002c/ssya002c.pdf TI JTAG Primer]
* [http://www.corelis.com/products/Boundary-Scan_Tutorial.htm JTAG Tutorial and Boundary-Scan Applications]
* [http://hri.sourceforge.net/tools/jtag_faq_org.html JTAG FAQ]
* [http://www.asset-intertech.com/products/free_resources.htm Free JTAG Resources]
* [http://www.think-silicon.com/ipgenius.php?module=jtag_wrap Free verilog JTAG TAP controller and Boundary Scan configurator]
* [http://www.openjtag.net OpenJTAG Wiki]
* [http://www.xjtag.com/support-jtag/jtag-high-level-guide.php Overview of JTAG technology] - Design for Testability (DFT) Guidelines, BGA, ISP; Chain Integrity, Connection & Functional Testing
* [http://www.xjtag.com/jtag-technical-guide.php Brief technical guide to JTAG Boundary Scan] - An overview of how JTAG is implemented. Signals, TAP controller, Registers, Instructions.
* [http://www.inaccessnetworks.com/ian/projects/ianjtag/jtag-intro/jtag-intro.html A Brief Introduction to the JTAG Boundary Scan Interface]


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