Branch misprediction

Branch misprediction

Branch misprediction occurs when a central processing unit (CPU) mispredicts the next instruction to process in branch prediction, which is aimed at speeding up execution.

During the execution of certain programs there are places where the program execution flow can continue in several ways. These are called branches, or conditional jumps. The CPU also uses a pipeline which allows several instructions to be processed at the same time. When the code for a conditional jump is read we do not yet know the next instruction to execute and insert into the execution pipeline. This is where branch prediction comes in.

Branch prediction guesses the next instruction to execute and inserts the next assumed instruction to the pipeline. Guessing wrong is called branch misprediction. The partially processed instructions in the pipeline after the branch have to be discarded and the pipeline has to start over at the correct branch when a branch misprediction is detected. This slows down the program execution.


Wikimedia Foundation. 2010.

Игры ⚽ Нужно сделать НИР?

Look at other dictionaries:

  • Branch predictor — In computer architecture, a branch predictor is the part of a processor that determines whether a conditional branch in the instruction flow of a program is likely to be taken or not. This is called branch prediction. Branch predictors are… …   Wikipedia

  • Register renaming — In computer engineering, register renaming refers to a technique usedto avoid unnecessary serialization of program operations imposed by the reuseof registers by those operations.Problem definitionPrograms are composed of instructions which… …   Wikipedia

  • Memory dependence prediction — is a technique, employed by high performance out of order execution microprocessors that execute memory access operations (loads and stores) out of program order, to predict true dependences between loads and stores at instruction execution time …   Wikipedia

  • Alpha 21064 — The 21064 microprocessor The 21064 microprocessor m …   Wikipedia

  • Memory disambiguation — is a set of techniques employed by high performance out of order execution microprocessors that execute memory access instructions (loads and stores) out of program order. The mechanisms for performing memory disambiguation, implemented using… …   Wikipedia

  • NetBurst (microarchitecture) — The NetBurst microarchitecture, called P68 inside Intel, was the successor to the P6 microarchitecture in the x86 family of CPUs made by Intel. The first CPU to use this architecture was the Willamette core of the Pentium 4, released on November… …   Wikipedia

  • Out-of-order execution — In computer engineering, out of order execution (OoOE or OOE) is a paradigm used in most high performance microprocessors to make use of instruction cycles that would otherwise be wasted by a certain type of costly delay. In this paradigm, a… …   Wikipedia

  • IBM RS64 — The IBM RS64 family of processors is used in the late 1990s for IBM s RS/6000 and AS/400 server product lines. The family is using an instruction set called Amazon , or PowerPC AS . It contains a subset of the PowerPC instruction set, with the… …   Wikipedia

  • Hyper-threading — (officially termed Hyper Threading Technology or HTT) is an Intel proprietary technology used to improve parallelization of computations performed on PC microprocessors via simultaneous multithreading. It is an improvement on super threading. It… …   Wikipedia

  • Decoupled architecture — In computer science, a decoupled architecture is a processor with out of order execution that separates the fetch and decode stages from the execute stage in a pipelined processor by using a buffer. The buffer s purpose is to partition the memory …   Wikipedia

Share the article and excerpts

Direct link
Do a right-click on the link above
and select “Copy Link”