Digital timing diagram

Digital timing diagram

A Digital timing diagram is a representation of a set of signals in the time domain. A timing diagram can contain many rows, usually one of them being the clock. It is a tool that is ubiquitous in digital electronics, hardware debugging, and digital communications. Besides providing an overall description of the timing relationships, the digital timing diagram can help find and diagnose digital logic hazards.

Diagram convention

Most timing diagrams use the following conventions:

  • Higher value is a logic one
  • Lower value is a logic zero
  • A slot showing a high and low is an either or (such as on a data line)
  • A Z indicates high impedance
  • A greyed out slot is a don't-care or indeterminate..

Example: SPI bus timing

A timing diagram for the Serial Peripheral Interface Bus

The timing diagram example on the right describes the Serial Peripheral Interface (SPI) Bus. Most SPI master nodes have the ability to set the clock polarity (CPOL) and clock phase (CPHA) with respect to the data. This timing diagram shows the clock for both values of CPOL as well as the values for the two data lines (MISO & MOSI) for each value of CPHA. Note that when CPHA=1 then the data is delayed by one-half clock cycle.


SPI operates in the following way:

  • The master determines an appropriate CPOL & CPHA value
  • The master pulls down the slave select (SS) line for a specific slave chip
  • The master clocks SCK at a specific frequency
  • During each of the 8 clock cycles the transfer is full duplex:
  • The master writes on the MOSI line and reads the MISO line
    • The slave writes on the MISO line and reads the MOSI line
  • When finished the master can continue with another byte transfer or pull SS high to end the transfer

When a slave's SS line is high then both of its MISO and MOSI line should be high impedance so to avoid disrupting a transfer to a different slave. Prior to SS being pulled low, the MISO & MOSI lines are indicated with a "z" for high impedance. Also prior to the SS being pulled low the "cycle #" row is meaningless and is shown greyed-out.

Note that for CPHA=1 the MISO & MOSI lines are undefined until after the first clock edge and are also shown greyed-out before that.

A more typical timing diagram has just a single clock and numerous data lines


Wikimedia Foundation. 2010.

Игры ⚽ Поможем написать реферат

Look at other dictionaries:

  • Timing diagram — may refer to:* Digital Timing Diagram * UML Timing Diagram …   Wikipedia

  • Diagram — Further information: Chart Sample flowchart representing the decision process to add a new article to Wikipedia. A diagram is a two dimensional geometric symbolic representation of information according to some visualization technique. Sometimes …   Wikipedia

  • Digital video testing — in broadcast video, for example, is the process of validating and verifying that the video content and other data is being correctly processed, stored and transported. Despite the fact that the data is digital, most digital tv (DTV) system… …   Wikipedia

  • Constellation diagram — A constellation diagram is a representation of a signal modulated by a digital modulation scheme such as quadrature amplitude modulation or phase shift keying. It displays the signal as a two dimensional scatter diagram in the complex plane at… …   Wikipedia

  • Pulse (signal processing) — In signal processing, the term pulse has the following meanings: #A rapid, transient change in the amplitude of a signal from a baseline value to a higher or lower value, followed by a rapid return to the baseline value. #A rapid change in some… …   Wikipedia

  • Phase-shift keying — Passband modulation v · d · e Analog modulation AM · …   Wikipedia

  • Flip-flop (electronics) — An SR latch, constructed from a pair of cross coupled NOR gates. Red and black mean logical 1 and 0 , respectively. In electronics, a flip flop or latch is a circuit that has two stable states and can be used to store state information. The… …   Wikipedia

  • UML — (англ. Unified Modeling Language  унифицированный язык моделирования)  язык графического описания для объектного моделирования в области разработки программного обеспечения. UML является языком широкого профиля, это  открытый… …   Википедия

  • Unified Modeling Language — UML (сокр. от англ. Unified Modeling Language  унифицированный язык моделирования)  язык графического описания для объектного моделирования в области разработки программного обеспечения. UML является языком широкого профиля, это открытый стандарт …   Википедия

  • Гради Буч — UML (сокр. от англ. Unified Modeling Language  унифицированный язык моделирования)  язык графического описания для объектного моделирования в области разработки программного обеспечения. UML является языком широкого профиля, это открытый стандарт …   Википедия

Share the article and excerpts

Direct link
Do a right-click on the link above
and select “Copy Link”