Intel Nehalem (microarchitecture)

Nehalem is the codename for an Intel processor microarchitecture. [cite press release
title = Intel Details Upcoming New Processor Generations
title = http://www.intel.com/pressroom/archive/releases/20070328fact.htm
publisher = Intel Corporate | date = 2007-03-28] , The first processor released with this architecturce is the desktop Core i7. [ cite web | url = http://www.tgdaily.com/content/view/38818/135/
title = Nehalem = i7: Intel unveils new Core processor brand
first = Wolfgang | last = Gruener | date = 2008-08-10 | publisher = tgdaily ] Nehalem will be released in late 2008 for high-end desktop and dual-processor platforms [cite web | url = http://uk.reuters.com/article/rbssTechMediaTelecomNews/idUKN2140939320080521
title = Intel says Nehalem chips on track for '08 2nd half
first = Scott | last = Hillis | coauthor = John Wallace
date = 2008-05-21 | publisher = Reuters ] and in Q4 2009 to Q1 2010 for mainstream desktop and mobile platforms. The microarchitecture is the successor to the Core microarchitecture.

Initial Nehalem processors use the 45 nm manufacturing methods from Penryn. A working system with two Nehalem processors was shown at Intel Developer Forum Fall 2007 [ cite web | url = http://www.anandtech.com/cpuchipsets/intel/showdoc.aspx?i=3101&p=2
title = IDF 2007 - Day 1: Nehalem, Intel's GPUs, 32nm and More
first = Anand | last = Lal Shimpi | date = 2007-09-18 | publisher | AnandTech] , and a large number of Nehalem systems were shown at Computex in June 2008.

The processor is named after the Nehalem River in Northwest Oregon, which is in turn named after the Nehalem Native American tribe in Oregon. The code name itself had been seen on the end of several roadmaps starting in 2000. At that stage it was supposed to be the latest evolution of the NetBurst architecture. Since the abandonment of NetBurst, the codename has been recycled and refers to a completely different project.

Technology

As described at Spring IDF 2008, Nehalem appears to incorporate the most significant new architectural changes to the x86 microarchitecture since the Pentium Pro debuted in 1995. Nehalem is highly scalable with different components for different tasks. Various sources have stated Nehalem's specification will have:
* Two, four, or eight cores
** 731 million transistors for the quad core variant
* From 45 nm move to 32 nm manufacturing process
* Integrated memory controller supporting DDR3 SDRAM and between one and six memory channelsFact|date=July 2008
* Integrated graphics processor (IGP) located off-die, but in the same CPU packagecite web
url=http://www.tech.co.uk/computing/upgrades-and-peripherals/processors/news/idf-not-all-intel-nehalem-cpus-single-die?articleid=629416659
title=IDF: Not all Intel Nehalem CPUs single-die
first=Jeremy | last = Laird | publisher=Tech.co.uk | date=2007-09-19]
* A new point-to-point processor interconnect, the Intel QuickPath Interconnect, replacing the legacy front side bus
* Simultaneous multithreading by multiple cores and hyperthreading, which enables two threads per core. Simultaneous multithreading has not been present on a consumer Intel processor since 2006 with the Pentium 4 and Pentium XE.
* Native (monolithic, i.e. all processor cores on a single die) quad- and octo-core (8) processors [cite web
url = http://www.tech.co.uk/computing/upgrades-and-peripherals/processors/news/idf-intel-reveals-eight-core-pc-processor?articleid=1878171680
title = IDF: Intel reveals eight-core PC processor
date = 2007-07-19 | first = Jeremy | last = Laird | publisher = TechRadar UK ]
* The following caches:
** 32 KB L1 instruction and 32 KB L1 data cache per core
** 256 KB L2 cache per core
** 2-3 MB L3 cache per core shared by all cores
* 33% more in-flight micro-ops than Conroecite web
url=http://www.anandtech.com/cpuchipsets/intel/showdoc.aspx?i=3264
title=Opening the Kimono: Intel Details Nehalem and Tempts with Larrabee
author=Anand | last = Lal Shimpi | publisher=AnandTech | date = 2008-03-17 ]
* Second-level branch predictor and second-level Translation Lookaside Buffer
* Modular blocks of components such as cores that can be added and subtracted for varying market segments [cite web
url=http://download.intel.com/pressroom/archive/reference/Gelsinger_briefing_0308.pdf
format=pdf
title=Intel Architecture Press Briefing
last=Gelsinger | first=Patrick P | work=Intel | date=2008-03-17 ]

Event demonstrations at the Shanghai Intel Developer Forum showed A1 silicon Bloomfield-based Nehalem processors at IDF running at 3.2 GHz. This processor had 32 KB L1 instruction and 32 KB L1 data cache, 256 KB L2 cache per core, and 8 MB of shared L3 cache. [cite web
url =http://xtreview.com/addcomment-id-4172-view-Intel-Nehalem-cpuz.html
title = Intel Nehalem cpuz | date = 2008-02-03 | publisher = Xtreview ]

Performance and power improvements

It has been reported that Nehalem will have a focus on performance, which accounts for the increased core size.cite web
url=http://pc.watch.impress.co.jp/docs/2008/0129/kaigai412.htm
language=Japanese | work=PC Watch
title=Intel's dual teamed approached to micro-architecture development | date=2008-01-29 ] Compared to Penryn, Nehalem will have:
*1.1x to 1.25x the single-threaded performance or 1.2x to 2x the multithreaded performance at the same power level
*30% lower power usage for the same performance
*According to a preview from "AnandTech" "expect a 20-30% overall advantage over Penryn with only a 10% increase in power usage. It looks like Intel is on track to delivering just that in Q4."cite web
url = http://anandtech.com/cpuchipsets/intel/showdoc.aspx?i=3326&p=9
first = Anand | last = Lal Shimpi
publisher = AnandTech | date = 2008-06-05
title = The Nehalem Preview: Intel Does It Again ]
*Core-wise, clock-for-clock, Nehalem will provide a 15%-20% increase in performance compared to Penryn. [http://www.canardplus.com/dossier-35-200-Processeur_de_Nehalem_a_Haswell.html]

"PC Watch" found that a Nehalem "Gainestown" processor has 1.6x the SPECint_rate2006 integer performance and 2.4x the SPECfp_rate_2006 floating-point performance of a 3.0 GHz Xeon X5365 "Clovertown" quad-core processor.

A 2.93 GHz Nehalem "Bloomfield" system has been used to run a 3DMark Vantage benchmark and gave a CPU score of 17,966. [cite web | url = http://www.tomshardware.co.uk/intel-nehalem-core,news-28701.html
title = 'Nehalem' 2.93 GHz Benches Revealed
first = Tuan | last =Nguyen | date = 2008-07-09 | publisher = Tom's Hardware ] The 2.66 GHz variant scores 16,294. A 2.4 GHz Core 2 Duo E6600 scores 4,300. [cite web
title = Intel Bloomfield 2.66 GHz: First Comprehensive Evaluation
url = http://www.techpowerup.com/?65297 | date = 2008-07-09 | publisher = techPowerUp! ]

"AnandTech" tested the Intel QuickPath Interconnect (4.8 GT/s version) and found the copy bandwidth using triple-channel 1066 MHz DDR3 was 12.0 GB/s. A 3.0 GHz Core 2 Quad system using dual-channel 1066 MHz DDR3 achieved 6.9 GB/s. [cite news
publisher = AnandTech
date= 2008-06-05
url=http://www.anandtech.com/cpuchipsets/intel/showdoc.aspx?i=3326&p=5
title=Intel does it again]

Overclocking will be possible with Bloomfield processors and the X58 chipset. The Lynnfield and Havendale processors will use a PCH removing the need for a northbridge chipset. [cite web
url = http://news.softpedia.com/news/Intel-No-Overclocking-for-Mainstream-Nehalems-84019.shtml
first = Bogdan | last = Botezatu | date = 2008-04-22
title = Intel: No Overclocking for Mainstream Nehalems | publisher = Softpedia ]

Variants

Nehalem will come in variants for servers, desktops, and notebooks. The four-socket server CPU is codenamed "Beckton", the two-socket server CPU is codenamed "Gainestown", and the single-socket desktop CPU is codenamed "Bloomfield". [cite web
url = http://www.reghardware.co.uk/2007/10/26/intel_roadmaps_extreme_nahelems/
first = Tony | last = Smith | date = 2007-10-26
title = Intel roadmaps next-gen Extreme 'Nehalem' chips
publisher =Register Hardware] Server processors will support registered DDR3.cite web
url=http://www.dailytech.com/Article.aspx?newsid=9823&red=y#217890
title=Gearing Up for "Nehalem" Sockets
author=Kristopher Kubicki | date=2007-11-28 | publisher=DailyTech]

Seven code names have been associated with the Nehalem microarchitecture in a PC Watch article.ja iconcite web
url=http://pc.watch.impress.co.jp/docs/2007/1128/kaigai403.htm
title=What GPU integration CPU of Intel "Havendale/Auburndale"? (translated title)
author=Hiroshige Goto | date=2007-11-28 | publisher=PC Watch ] These include two server processors, three desktop processors, and two mobile processors. The server processor, "Beckton", will have 44 bits of physical memory address and 48 bits of virtual memory address. The mainstream and value processor, "Havendale", will have a FDI bus. [cite web
url = http://www.fudzilla.com/index.php?option=com_content&task=view&id=8484&Itemid=1
title = More Nehalem details emerge
first = Lars-Göran | last = Nilsson | date = 2008-07-17 | publisher = Fudzilla ] It has been said that "Havendale" will have two different IGP versions [http://www.fudzilla.com/index.php?option=com_content&task=view&id=8799&Itemid=1] and at least six different parts, possibly six different frequencies. [http://www.fudzilla.com/index.php?option=com_content&task=view&id=8932&Itemid=1] It will also replace both dual-core and quad-core Penryn CPUs. [http://www.nordichardware.com/news,8101.html] Intel has confirmed that there will be at least four different variants of Nehalem CPUs. One variant is Core i7 while two others are slated for 2009 as dual- and quad-core. [http://www.fudzilla.com/index.php?option=com_content&task=view&id=9447&Itemid=1]

Note: "Extreme" processors have an unlocked clock multiplier. TDP values for CPUs with integrated GPUs include the GPU. Prices are for batches of 1000.

uccessor

Westmere (formerly Nehalem-C) is the name given to the 32 nm shrink of "Nehalem". "Westmere" should be ready for a 2009 release provided that Intel stays on target with its roadmap. However, it appears that the bulk of Westmere's versions, excluding mobile versions, will be released sometime in 2010. [http://pc.watch.impress.co.jp/docs/2008/0326/kaigai02.pdf] ] [http://pc.watch.impress.co.jp/docs/2008/0321/kaigai_10.pdf] ] From various sources, Westmere's changes and improvements from Nehalem have been reported as follows:

* 32 nm process.
* Native six-core processors.
** The successor to Bloomfield and Gainestown is either quad-core or six-core.
* A new set of instructions that gives over 3x the encryption and decryption rate of AES processes compared to before.cite web
url=http://www.bit-tech.net/news/2007/09/19/westmere_is_nehalem_successor/1
title=Westmere is Nehalem's successor
first =Tim | last = Smalley | date=2007-09-19 | publisher=bit-tech.net]
** Delivers six new instructions that will be used by the Advanced Encryption Standard (AES) algorithm and also an instruction that will perform carry-less multiplication (PCLMULQDQ). Those instructions allow the processor to perform hardware accelerated encryption not only providing a faster execution but also protects against software targeted attacks.
** AES-NI may be included in the integrated graphics of Westmere.
* Westmere's integrated graphics may be released at the same time as the processor.
* Improved virtualization latency. [http://www.fudzilla.com/index.php?option=com_content&task=view&id=9448&Itemid=1]
* Release dates:
** Q4 2009 to January 2010 for mobile chips. [http://en.expreview.com/2008/09/04/lynnfield-has-powered-on-and-booted-linux-windows-prepare-for-holiday-refresh-2009] ]
** Late 2009 or early 2010 for DP server chips. [http://pc.watch.impress.co.jp/docs/2008/0513/kaigai_3.pdf] ]
** H1 2010 for high-end desktop chips (Bloomfield successor).
** H2 2010 for mainstream and value desktop chips, assuming Westmere is released for that segment.

The successor to "Westmere" will be Sandy Bridge, scheduled for release in 2010, according to Intel roadmaps. [cite web
url = http://www.intel.com/technology/tick-tock/index.htm
title = The Intel Tick-Tock Model of Architecture & Silicon Cadence | publisher = Intel Corporation ]

Then, the successor to "Sandy Bridge" will be Haswell, scheduled for release in 2012. It will come with a new cache subsystem, a FMA (fused multiply-add) unit, and a vectorial coprocessor [cite web
url = http://www.canardplus.com/dossier-35-200-Processeur_de_Nehalem_a_Haswell.html
title = IDF 2008 Shanghaï - From Nehalem to Haswell | publisher = Canard PC (French) ]

See also

* x86 architecture
* x86-64
* P5
* P6
* Netburst
* Core
* Sandy Bridge
* Haswell
* List of Intel CPU microarchitectures

References

Further reading

* cite web
url = http://xtreview.com/addcomment-id-6524-view-Intel-core-i-7-940-review.html
title = Intel Nehalem Core i7 940 Review
publisher = Xtreview | date = 2008-10-01
* cite web
url = http://www.hothardware.com/Articles/Intel_Showcases_Dunnington_Nehalem_and_Larrabee_Processors/
title = Intel Showcases Dunnington, Nehalem and Larrabee Processors
publisher = HotHardware | date = 2008-03-17 | first = Dave | last = Altavilla
* cite web
url = http://www.pcper.com/article.php?aid=382&type=expert
title = Intel Slides and Nehalem architecture information
publisher = PC Perspective | date = 2008-03-28 | first = Ryan | last = Shrout
* cite web
url = http://arstechnica.com/news.ars/post/20070328-intel-aims-nehalem-at-amds-fusion-integrated-graphics-on-die-memory-controller-smt.html
title = Intel drops a Nehalem bomb on AMD's Fusion: integrated graphics, on-die memory controller, SMT
publisher = Ars Technica | date = 2007-03-28 | first = Jon | last = Stokes
* cite web
url = http://www.anandtech.com/cpuchipsets/intel/showdoc.aspx?i=3101&p=2
title = Nehalem: Single die, 8-cores, 731M transistors
publisher = AnandTech | date = 2007-09-18 | first = Anand | last = Lal Shimpi
* cite web
url = http://www.itpro.co.uk/news/125370/idf-2007-intel-debuts-nehalem.html
title = IDF 2007: Intel debuts Nehalem
publisher = IT Pro | date = 2007-09-19 | first = Maggie | last = Holland
* cite web
url = http://www.jpost.com/servlet/Satellite?c=JPArticle&cid=1192380801327&pagename=JPost%2FJPArticle%2FShowFull
title = Intel takes the silicon out of chips
publisher = Jerusalem Post | date = 2007-11-13 | first = Matthew Krieger
* cite web
url = http://www.chw.net/Articulos/Intel/Todo-lo-que-sabemos-de-Intel-Nehalem-200801051919.html
title = Everything we know about Nehalem | language = Spanish
publisher = CHW.net | date = 2008-01-05
* cite web
url = http://xtreview.com/addcomment-id-4164-view-Bloomfield-will-cost-less-than-400-dollars.html
title = Bloomfield will cost less than 400 dollars
publisher = Xtreview | date = 2008-02-01
* cite web
url = http://arstechnica.com/articles/paedia/cpu/what-you-need-to-know-about-nehalem.ars
title = What you need to know about Intel's Nehalem CPU
publisher = Ars Technica | date = 2008-04-09 | first = Jon | last = Stokes
* cite web
url = http://www.hardwaresecrets.com/article/535
title = Details on the Forthcoming Intel Nehalem Processor
publisher = Hardware Secrets | date = 2008-03-17 | first = Gabriel | last = Torres
* cite web
url = http://realworldtech.com/includes/templates/articles.cfm?ArticleID=RWT040208182719&mode=print
title = Real World Technologies article on Nehalem's microarchitecture
publisher = Real World Technologies | date = 2008-04-02 | first = David | last = Kanter
* cite web
url = http://www.anandtech.com/cpuchipsets/intel/showdoc.aspx?i=3326
title = The Nehalem Preview: Intel Does It Again
publisher = AnandTech | date = 2008-06-05 | first = Anand Lal | last = Shimpi
* cite web
url = http://www.anandtech.com/cpuchipsets/intel/showdoc.aspx?i=3382
title = Nehalem - Everything You Need to Know about Intel's New Architecture
publisher = AnandTech | date = 2008-08-21 | first = Anand Lal | last = Shimpi
* cite web
url = http://www.hardware-infos.com/berichte.php?bericht=36
title = Intel Nehalem-Architektur
publisher = Hardware-Infos | date = 2008-09-20