PA-7200

The PA-7200 (PCX-T'), code-named Thunderbird', is a microprocessor that implements the PA-RISC 1.1 instruction set architecture (ISA) developed by Hewlett-Packard (HP). It was introduced in early 1995, debuting in systems from HP. The PA-7200 was not sold openly and the only third-party users were Convex Computer and Stratus Computer, both members of the Precision RISC Organization (PRO). It was developed for small multiprocessing systems with two or four microprocessors. The microprocessor was first described at the Compcon and IEEE International Solid-State Circuits Conference (ISSCC) conferences.

Description

The PA-7200 was mostly derived from the PA-7100 and was improved adding a second integer unit, enabling it to issue up to two integer instructions per cycle. The second integer unit was not identical to the first, and only was only capable of executing simple but more frequently used instructions.

The PA-7200 contained 1.3 million transistors and measured 14.0 mm by 15.0 mm (210 mm²).^[1] It was fabricated by Hewlett-Packard in their CMOS14A process which they co-developed with Analog Devices.^[2] CMOS14A was a 0.55 µm, three-level interconnect, complementary metal–oxide–semiconductor (CMOS) process.

The microprocessor uses an unusual 4.4 V power supply as a result of its development.^[2] It was designed in the 0.8 µm CMOS26B process and leveraged circuits and layouts from the PA-7100, which was also designed for CMOS26B. The completed design was then shrunk for the 0.55 µm CMOS14A process. This process has 120-angstrom gate oxide that did not tolerate 5.0 V operation. A 3.3 V power supply did not enable the microprocessor to achieve the intended clock frequency, so 4.4 V was chosen as a compromise.

Notes

1. ^ "Design of the HP PA 7200 CPU", p. 2.
2. ^ ^{a b} "PA-7200 Enables Inexpensive MP Systems", p. 3.

References

• Chan, Kenneth K.; et al. (February 1996). "Design of the HP PA 7200 CPU". Hewlett-Packard Journal, February 1996.
• Gwennap, Linley (7 March 1994). "PA-7200 Enables Inexpensive MP Systems". Microprocessor Report, Volume 8, Number 3.
• Pountain, Dick (August 1994). "A Different Kind of RISC". Byte.
• PA-7200 PA-RISC Processor OpenPA.net

Further reading

• Rashid, E.; et al. (1994). "A CMOS RISC CPU with on-chip parallel cache". ISSCC Digest of Technical Papers.