Clipper architecture

Not to be confused with Clipper chip.

Intergraph Clipper C4 (C400) CPU

The Clipper architecture is a 32-bit RISC-like instruction set architecture designed by Fairchild Semiconductor. The architecture never enjoyed much market success, and the only computer manufacturers to create major product lines using Clipper processors were Intergraph and High Level Hardware. The first processors using the Clipper architecture were designed and sold by Fairchild, but the division responsible for them was subsequently sold to Intergraph in 1987; Intergraph continued work on Clipper processors for use in its own systems.

The Clipper architecture used a simplified instruction set compared to earlier CISC architectures, but it did incorporate some more complicated instructions than were present in other contemporary RISC processors. These instructions were implemented in a so-called Macro Instruction ROM within the Clipper CPU. This scheme allowed the Clipper to have somewhat higher code density than other RISC CPUs.

Versions

The initial Clipper microprocessor produced by Fairchild was the C100, which became available in 1986. This was followed by the faster C300 from Intergraph in 1988. The final model of the Clipper was the C400, released in 1990, which was extensively redesigned to be faster and added more floating-point registers. The C400 processor combined two key architectural techniques to achieve a new level of performance — superscalar instruction dispatch and superpipelined operation.

Intergraph started work on a subsequent Clipper processor design known as the C5, but this was never completed or released. Nonetheless, some advanced processor design techniques were devised for the C5, and Intergraph was granted patents on these. These patents, along with the original Clipper patents, have been the basis of patent-infringement lawsuits by Intergraph against Intel and other companies.

Unlike many other microprocessors, the Clipper processors were actually sets of several distinct chips. The C100 and C300 consist of three chips: one central processing unit containing both an integer unit and a floating point unit, and two cache and memory management units (CAMMUs), one responsible for data and one for instructions. The CAMMUs contained caches, translation lookaside buffers, and support for memory protection and virtual memory. The C400 consists of four basic units: an integer CPU, an FPU, an MMU, and a cache unit. The initial version used one chip each for the CPU and FPU and discrete elements for the MMU and cache unit, but in later versions the MMU and cache unit were combined into one CAMMU chip.

Intergraph's Clipper systems

Photograph of an Intergraph CLIX workstation

Intergraph sold several generations of Clipper systems, including both servers and workstations. These systems included the InterAct, InterServe, and InterPro product lines and were targeted largely at the CAD market.

Fairchild promoted the CLIX operating system, a version of UNIX System V, for use with the Clipper. Intergraph adopted CLIX for its Clipper-based systems and continued to develop it; this was the only operating system available for those systems. Intergraph did work on a version of Microsoft Windows NT for Clipper systems and publicly demonstrated it, but this effort was canceled before release. [1] Intergraph decided to discontinue the Clipper line and began selling x86 systems with Windows NT instead.

References

• Fairchild Semiconductor Corporation (1987). CLIPPER 32-Bit microprocessor: User's Manual. Prentice-Hall. ISBN 0-13-138058-3. 
• Walter Hollingsworth, Howard Sachs, and Alan Jay Smith (1989). "The CLIPPER Processor: Instruction Set Architecture and Implementation". Communications of the ACM 32 (2): 200–219. doi:10.1145/63342.63346.  [2]
• Walter Hollingsworth; Howard Sachs and Alan Jay Smith (February 11, 1987). The Fairchild CLIPPER: Instruction Set Architecture and Processor Implementation (Technical report). UCB/CSD. 87/329. http://www.eecs.berkeley.edu/Pubs/TechRpts/1987/CSD-87-329.pdf. Retrieved 2011-03-22. 
• James Cho; Alan Jay Smith and Howard Sachs (April 1986). The Memory Architecture and the Cache and Memory Management Unit for the Fairchild CLIPPER Processor (Technical report). UCB/CSD. 86/289. http://www.eecs.berkeley.edu/Pubs/TechRpts/1986/CSD-86-289.pdf. Retrieved 2011-03-22. 
• Howard Sachs, Harlan McGhan, Lee Hanson, and Nathan Brookwood (1991). "Design and Implementation Trade-offs in the Clipper C400 Architecture". IEEE Micro 11 (3): 18–21, 74–80. doi:10.1109/40.87566.  [3]
• Intergraph history