VIA Nano

Infobox Computer Hardware Cpu
name = VIA Nano


size-from = 0.065
size-to = 0.045
fsb-slowest = 800 | fsb-slow-unit = MT/s
fsb-fastest = 1333 | fsb-fast-unit = MT/s
soldby = VIA Technologies
designfirm = Centaur Technology
manuf1 = Fujitsu
manuf2 = TSMC
core1 = Isaiah (CN)
sock1 = Ball grid array (Soldered)
arch = x86-64
microarch = VIA Isaiah
numcores = 1 (2 or more in the future)The VIA Nano (formerly codenamed VIA Isaiah) is a 64-bit central processing unit for personal computers released by VIA Technologies in 2008 after five years of development [cite web
title = VIA to launch new processor architecture in 1Q08
publisher = DigiTimes.
url = http://www.digitimes.com/news/a20070725PD206.html
accessdate = 2007-07-25] by its CPU division, Centaur Technology. This new Isaiah 64-bit architecture was designed from scratch, unveiled on 24 January 2008 [cite web
title = Isaiah revealed: VIA's new low-power architecture
publisher = ArsTechnica.com
url = http://arstechnica.com/articles/paedia/cpu/via-cpu-isaiah.ars
accessdate = 2008-01-24] [cite web
title = VIA's New Centaur Designed Isaiah CPU Architecture
publisher = HardOCP.com
url = http://enthusiast.hardocp.com/article.html?art=MTQ1MCwxLCxoZW50aHVzaWFzdA=

accessdate = 2008-01-24] [cite web
title = Via launches 64-bit architecture
publisher = LinuxDevices.com
url = http://www.linuxdevices.com/news/NS5877802443.html
accessdate = 2008-01-24] [cite web
title = A look at VIA's next-gen Isaiah x86 CPU architecture
publisher = TechReport.com
url = http://techreport.com/articles.x/13996
accessdate = 2008-01-24] , and launched on May 29, including low voltage variants and the Nano brandname. [cite web
title = VIA Launches VIA Nano Processor Family
publisher = VIA
url = http://www.via.com.tw/en/resources/pressroom/pressrelease.jsp?press_release_no=2369
accessdate = 2008-05-29]

Unlike Intel and AMD, VIA uses two distinct development codenames for each of its CPU cores. In this case, the codename 'CN' was used in the U.S. by Centaur Technology. Biblical names are used as codes by VIA in Taiwan, and Isaiah the choice for this particular processor and architecture. It is expected that the VIA Isaiah is twice as fast in integer performance and four times as fast in floating-point performance as previous-generation VIA Esther at an equivalent clock speed. Power consumption is also expected to be on par with the previous generation VIA CPUs, with Thermal Design Power ranging from 5W to 25W. [cite web
publisher = VIA
url = http://www.via.com.tw/en/downloads/presentations/processors/pb_via-isaiah_080124.pdf
title = VIA Isaiah Architecture Introduction
accessdate = 2008-05-28] Being a completely new design, the Isaiah architecture was built with support for features like the x86-64 instruction set and virtualization technology which were unavailable on previous VIA microprocessors such as the C7 line, while retaining the C7 encryption extensions.

At a glance

* Codename "CN".
* x86-64 instructions architecture
* 65nm or 45nm manufacturing process
* 25W TDP at 2.0GHz
* V4 bus speed of 800MHz~1333MHz
* Support for ECC
* Virtualization technology (Intel compatible implementation)
* 128KB L1 cache like the previous generation and 1MB L2 cache, exclusive
* Pin compatible with the VIA C7.

Architecture Improvements

* Out-of-order and superscalar design: Providing much better performance than its predecessor, the VIA C7 processor, which was in-order. This puts the Isaiah architecture in line with current offerings from AMD and Intel, except for Intel Atom which has an in-order design.
* Instructions fusion: Allows to combine some instructions as a single instruction to reduce power requirements and give a higher performance.
* Improved branch prediction: Uses eight predictors in two pipeline stages.
* Cache design: An exclusive cache design means that contents of the L1 cache is not duplicated in the L2 cache, providing a larger total cache.
* Data prefetch: Incorporating new mechanisms for data-prefetch, including both the loading of a special 64-line cache before loading the L2 cache and a direct load to the L1 cache.
** Fetches 4 x86 instructions per cycle as opposed to Intel's 3-5
** Issues 3 uinst/clock to execution units
* Memory access: Merging of smaller stores into larger load data.
* Execution units: Seven execution units are available, that allows up to seven micro-ops being executed per clock.
** 2 Integer units
*** One unit (ALU1) is feature complete, while the other (ALU2) lacks some low usage instructions and therefore can be used more often for tasks like address calculations.
** 2 Store units (VIA refer to this as one for Address Store and another for Data Store)
** 1 Load unit
** 2 Media units with 128-bit wide datapath, supporting 4 single precision or 2 double-precision operations.
*** One unit (MEDIA-A) correspond to floating point support, 2-clock latency for single-precision and double-precision add instructions, integer SIMD, encryption, divide and square root.
*** The other unit (MEDIA-B) performs single-precision multiplies, with 3-clock latency for double-precision multiplies.
* Media computation: Refers to the use of floating point execution units.
** Using an execution unit for floating point computation and another for multiplication allows the execution of up to four floating point and four multiplies per clock.
** A new implementation of FP-addition with the lowest latency (in clocks) seen in x86 processors so far.
** Almost all integer SIMD instructions execute in one clock.
** Implements MMX, SSE, SSE2, SSE3, SSSE3 multimedia instruction sets
* Power Management: Besides requiring very low power, many new features are included.
** Includes a new C6 power state (Caches are flushed, internal state saved, and core voltage is turned off).
** "Adaptive P-State Control": Transition between performance and voltage states without stopping execution.
** "Adaptive Overclocking": Automatic overclocking if there is low temperature in the processor core.
** "Adaptive Thermal Limit": Adjusting of the processor to maintain a user predefined temperature.
* Encryption: Includes the VIA PadLock engine
** Hardware support for Advanced Encryption Standard encryption, SHA-1 and SHA-256 hashing

ee also

*List of VIA Nano microprocessors
*List of VIA microprocessors
*Netbook

References

External links

* [http://www.via.com.tw/en/products/processors/nano/ VIA Nano Processor]
* [http://www.via.com.tw/en/downloads/whitepapers/processors/WP080529VIA_Nano.pdf VIA Nano Processor Introductory White Paper]

Press

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