PMOS logic

pMOS logic uses p-type metal-oxide-semiconductor field effect transistors (MOSFETs) to implement logic gates and other digital circuits. pMOS transistors have three modes of operation: cut-off, triode, and saturation (sometimes called active).

The p-type MOSFETs are arranged in a so-called "pull-up network" (PUN) between the logic gate output and positive supply voltage, while a resistor is placed between the logic gate output and the negative supply voltage. The circuit is designed such that if the desired output is high, then the PUN will be active, creating a current path between the positive supply and the output.

While pMOS logic is easy to design and manufacture (a MOSFET can be made to operate as a resistor, so the whole circuit can be made with pMOSFETs), it has several shortcomings as well. The worst problem is that a DC current flows through a pMOS logic gate when the PUN is active, that is whenever the output is high. This leads to static power dissipation even when the circuit sits idle.

Also, pMOS circuits are slow to transition from high to low. When transitioning from low to high, the transistors provide low resistance, and the capacitative charge at the output drains away very quickly. But the resistance between the output and the negative supply rail is much greater, so the high to low transition takes longer. Using a resistor of lower value will speed up the process but also increases static power dissipation.

Additionally, the asymmetric input logic levels make pMOS circuits susceptible to noise.

Though initially easier to manufacture, pMOS logic was supplanted by nMOS logic because nMOS is faster than pMOS.