Post silicon validation

Post-silicon validation and debug is the last step in the development of a semiconductor integrated circuit. During the pre-silicon process, engineers test devices in a virtual environment with sophisticated simulation, emulation, and formal verification tools. In contrast, post-silicon validation tests occur on actual devices running at-speed in commercial, real-world system boards using logic analyzer and assertion-based tools.

Large semiconductor companies spend millions creating new components; these are the "sunk costs" of design implementation. Consequently, it is imperative that the new chip function in full and perfect compliance to its specification, and be delivered to the market within tight consumer windows. Even a delay of a few weeks can cost tens of millions of dollars. Post-silicon validation is therefore one of the most highly leveraged steps in successful design implementation.

Chips comprising 500,000 logic elements are the silicon brains inside cell phones, MP3 players, computer printers and peripherals, digital television sets, medical imaging systems, components used in transportation safety and comfort, and even building management systems. Either because of their broad consumer proliferation, or because of their mission-critical application, the manufacturer must be absolutely certain that the device is thoroughly validated.

The best way to achieve high confidence is to leverage the pre-silicon verification work — which can comprise as much as 30% of the overall cost of the implementation — and use that knowledge in the post-silicon system. Today, much of this work is done manually, which partially explains the high costs associated with system validation. However, there are some tools that have been recently introduced to automate post-silicon system validation.

Simulation-based design environments enjoy the tremendous advantage of nearly perfect observability, meaning the designer can see any signal at nearly any time. They suffer, however, from the restricted amount of data they can generate during post-silicon system validation. Many complicated devices indicate their problems only after days or weeks of testing, and they produce a volume of data that would take centuries to reproduce on a simulator. FPGA-based emulators, a well-established part of most implementation techniques, are faster than software simulators but will not deliver the comprehensive at-system-speed tests needed for device reliability.

Moreover, the problem of post-silicon validation is getting worse, as design complexity increases because of the terrific advances in semiconductor materials processing. The duration from prototype silicon — so-called "first silicon" — to volume production is increasing, and bugs do escape to the customers. The expense associated with IP-hardening is increasing. The industry today is focused on techniques that allow designers to better amortize their investment in pre-silicon verification to post-silicon validation. The best of these solutions enable affordable, scalable, automated, on-chip wire-scale visibility.

ee also

*Electronic design automation
*List of EDA companies
*Design flow (EDA)

External links

* [http://www.edadesignline.com/howto/201806804;jsessionid=NXHPZSFX1BEDKQSNDLPSKHSCJUNN2JVN A New Approach to In-System Silicon Validation and Debug]
* [http://download.intel.com/technology/itj/q12001/pdf/art_3.pdf Validating the Intel Pentium 4 Processor]
* [http://www.chipdesignmag.com/display.php?articleId=1915&issueId=25 Improved IP-Centric Post-Silicon Validation Solutions Create A New IP Opportunity]
* [http://www.scdsource.com/article.php?id=83 On-chip validation extends IC verification]
* [http://www.us.design-reuse.com/articles/article5252.html Diagnostics for Design Validation]