Intel Sandy Bridge (microarchitecture)

. Intel has stated that they "are evaluating options to adjust Sandy Bridge schedule to ensure sufficient Nehalem lifecycle," and due to some Nehalem variants to be released in 2010, Sandy Bridge may be released later than originally planned. [http://en.expreview.com/2008/09/04/lynnfield-has-powered-on-and-booted-linux-windows-prepare-for-holiday-refresh-2009/]

Keifer

Previously it was said that in the 2010 timeframe Intel would release a highly multi-core DP server processor codenamed "Gulftown", from the Keifer project. [ [http://www.tgdaily.com/content/view/27460/135/ TGDaily - Intel aims for 32 cores by 2010] ]
*32 nm process.
*8 "nodes"/processor.
**4 cores/node (32 cores).
***4 threads/core (128 threads).
*2 GHz clock speed or higher.
*512 KB L2 cache/node.
*3 MB last level cache/node (24 MB total).
*Ring bus that connects the last level caches.
*2009-2010 release timeframe.
*A 15x performance improvement over the Xeon 5100.
*Aimed at Sun's UltraSPARC T1 and its successors. However, Keifer was cancelled shortly after it started. [ [http://www.tomshardware.com/reviews/project-keifer-32-core,1280-5.html TH - Every Node Gets Its Memory Controllers] ] [ [http://www.theinquirer.net/en/inquirer/news/2006/07/03/new-from-intel-its-mini-cores INQ - New from Intel: It's Mini-Cores!] ]

Architecture

Sandy Bridge's specifications are reported to be as follows, according to a presentation made by Intel in December 2006: [cite web |last=Davis|first=Ed|pages=Slide #31|title=Tera Tera Tera|url=http://bt.pa.msu.edu/TM/BocaRaton2006/talks/davis.pdf|accessdate=2007-06-01] [ [http://forums.vr-zone.com/showpost.php?p=3785868&postcount=1 vr-zone forum - Intel Larrabee GPU vs Gesher CPU] ] [ [http://arstechnica.com/news.ars/post/20070604-clearing-up-the-confusion-over-intels-larrabee-part-ii.html ars - Clearing up the confusion over Intel's Larrabee, part II] ] These specifications share similarities with the cancelled Gulftown processor.

*4 GHz clock speed.
*4 to 8 out-of-order cores.
*Without SSE: 8 DP GFLOPS/core (2 DP FP/clock), 32-64 DP GFLOPS/processor.
*With SSE: 28 DP GFLOPS/core (7 DP FP/clock), 112-224 DP GFLOPS/processor.
*32 KB L1 cache/core, (3 clocks).
*512 KB L2 cache/core, (9 clocks).
*2-3 MB L3 cache/core (8-24 MB total) (33 clocks), most likely pooled and dynamically allocated among the cores.
*64 bytes cache line width.
*256 bytes/cycle Ring bus bandwidth. The ring bus connects the cores.
*0-512 MB GDDR / fast DRAM.
*64 GB/s GDDR / fast DRAM memory bandwidth.
*17 GB/s memory bandwidth per QuickPath link with 50 ns latency.

According to a PC Watch article: [ [http://pc.watch.impress.co.jp/docs/2008/0129/kaigai412.htm 2つのCPU開発チームに競わせるIntelの社内戦略] ]
*Sandy Bridge will focus on power efficiency.
*Performance will be increased without a core size increase (similar to the Netburst to Core transition).
*Due to the small 32 nm process, the floating point unit is relatively small compared to the rest of the core.
*Dynamic Turbo allows the CPU power to exceed the TDP value when the rest of the platform is relatively cool. The frequency gain can be up to 37% for one minute, and over 20% in most cases.
*Nehalem may stay at the server platform while Sandy Bridge is released for the mobile segments, which would split the markets into two CPU lines.
*Sandy Bridge's CPU and GPU are likely to be on one die (unlike the two-die approach of Nehalem).
*Because of the high-performing CPU and off-chip components, it may be necessary to improve bus interconnects.
*The Sandy Bridge microarchitecture is also said to focus on the connections of the processor core.

The mobile Sandy Bridge version is expected to be released at the same time as the microarchitecture, which would mean a relatively short 1-year life of mobile Nehalem. [ [http://pc.watch.impress.co.jp/docs/2008/0602/kaigai442.htm ソケット数の制約から脱却するNehalem世代のIntel CPU] ] The platform chipset's northbridge is referred to as the 'Sandy Bridge System Agent' rather than 'MCH'. [ [https://intel.taleo.net/servlets/CareerSection?art_ip_action=FlowDispatcher&flowTypeNo=13&pageSeq=2&reqNo=205916&art_servlet_language=en&selected_language=en&csNo=10000#topOfCsPage Intel Career Section - Job description: System Validation Engineer – 550561] ]

Intel has said that Sandy Bridge will have new instructions called Advanced Vector Extensions (AVX). [cite web | url=http://www.extremetech.com/article2/0,1697,2276802,00.asp | title=Intel Offers Peek at Nehalem and Larrabee | author=Jason Cross | date=March 17, 2008 | publisher=ExtremeTech] These instructions are an advanced form of SSE. The data path is widened from 128 bits to 256 bits, the two-operand instruction limit is increased to four operands, and advanced data rearrangement functions are included. AVX is suited for floating-point-intensive applications. [ [http://www.pcper.com/article.php?aid=534&type=expert&pid=3 Intel IDF Preview: Tukwilla, Dunnington, Nehalem and Larrabee] ] Features of AVX include mask loads, data permutes, increased register efficiency and use of parallel loads, as well as smaller code size. The improvements of AVX will allow it to deliver up to double the peak FLOPS compared to before. Sandy Bridge will also have a VEX extensible new opocode [http://www.tgdaily.com/content/view/38891/135/ TGDaily] ]

Variants

The MP server (EX) version of Sandy Bridge is to be released at the start of 2011. [http://microboy.seesaa.net/article/95885389.html]

The DP server (EP) version of Sandy Bridge is to have 6 cores and 12 threads. It is to be released at the start of 2011. [http://microboy.seesaa.net/article/95885389.html]

A version of Sandy Bridge with 8 cores (16 threads) and 16 MB L3 cache is expected. [cite web |last=Doc |first=TB|title=IDF Shanghaï : From Nehalem to Haswell |url=http://www.canardplus.com/dossier-35-200-Processeur_de_Nehalem_a_Haswell.html|publisher=CanardPC (French) ]

Future

In keeping with its tick-tock principle, the 22 nm shrink of Sandy Bridge is due out in 2011 and will be called Ivy Bridge. The native 22 nm architecture that follows Ivy Bridge is Haswell. [cite web |last=Doc |first=TB|title=IDF Shanghaï : From Nehalem to Haswell |url=http://www.canardplus.com/dossier-35-200-Processeur_de_Nehalem_a_Haswell.html|publisher=CanardPC (French) ] [ [http://computerworld.co.nz/news.nsf/tech/41076B60BD096CC5CC25740400135E28 Intel to deliver six-core Xeon processor this year] ]

References

External links

* [http://softwareprojects.intel.com/avx/ Intel's AVX page]

ee also

* x86
* x86-64
* P5
* P6
* NetBurst
* Core
* Nehalem
* List of Intel CPU microarchitectures