- Back side bus
In
personal computer microprocessor architecture, a back side bus (BSB), or backside bus, is acomputer bus used to connect the CPU to CPU cache memory, usually L2. If a design utilizes it along with afront side bus (FSB), it is said to use a dual-bus architecture, or inIntel 's terminology "Dual Independent Bus" (DIB) [cite web|url=http://www.pcguide.com/ref/cpu/arch/extBackside-c.html|title=Dedicated Backside Cache Bus|publisher=PCguide.com|date=2001-04-30] architecture.BSB is an improvement over the older practice of accessing the cache over the front side bus (FSB), because FSB is typically a severe bottleneck in modern systems. In addition, due to its dedicated nature, the back side bus can be optimized or customized for communication with cache, thus eliminating protocol overheads and additional signals that are required on a general-purpose FSB. Furthermore, since a BSB operates over a shorter distance, it can typically operate at higher clock speeds, increasing the computer's overall performance.
Cache connected with a BSB was initially external to the CPU
silicon chip , but now is usually on-chip. [cite web
url=http://www.itworld.com/Comp/1091/CWD010430STO60015/
title=Buses: frontside and backside
publisher="ITworld "
date=2001-04-30] In the latter case, the BSB clock frequency is typically equal to the processor's,fact|date=September 2007 and the back side bus can also be made much wider (256-bit, 512-bit) than either off-chip or on-chip FSB.The dual-bus architecture has been used in a number of chips, including the
IBM andFreescale PowerPC processors (certain PowerPC 604 models, the G3 line based on thePowerPC 750 [cite web|url=http://news.com.com/Monday+a+big+day+for+Apple/2100-1001_3-205119.html|title=Monday a big day for Apple|publisher=CNet|date=1997-11-07] , and theFreescale G4 line), as well as theIntel Pentium II processor [cite web
url=http://searchstorage.techtarget.com/sDefinition/0,,sid5_gci213804,00.html
title=Backside Bus
publisher=Whatis.com
date=2001-04-30] , which used it to access their L2 cache (earlier Intel processors accessed the L2 cache over the FSB, while later processors moved it on-chip).ee also
*
CPU cache
*Computer bus
*Front side bus References
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