Register transfer language

In computer science, register transfer language (RTL) is a term used to describe a kind of intermediate representation (IR) that is very close to assembly language, such as that which is used in a compiler. Academic papers and textbooks also often use a form of RTL as an architecture-neutral assembly language. RTL is also the name of a specific IR used in the GNU Compiler Collection, and several other compilers, such as Zephyr [ [http://www.cs.virginia.edu/zephyr/vpoi/intro.html Zephyr Code-Generation Interfaces] ]

RTL in GCC

In GCC, RTL is generated from the GIMPLE representation, transformed by various passes in the GCC 'middle-end', and then converted to assembly language.

GCC's RTL is usually written in a form which looks like a Lisp S-expression:

: (set:SI (reg:SI 140) (plus:SI (reg:SI 138) (reg:SI 139)))

This "side-effect expression" says "add the contents of register 138 to the contents of register 139 and store the result in register 140."

The sequence of RTL generated has some dependency on the characteristics of the processor for which GCC is generating code. However, the meaning of the RTL is more-or-less independent of the target: it would usually be possible to read and understand a piece of RTL without knowing what processor it was generated for. Similarly, the meaning of the RTL doesn't usually depend on the original high-level language of the program.

A register transfer language is a system for expressing in symbolic form the microoperation sequences among the registers of a digital module. It is a convenient tool for describing the internal organization of digital computers in concise and precise manner. It can also be used to facilitate the design process of digital systems.

RTL as it relates to logic synthesis

RTL is commonly used in the electronics design industry to refer to the coding style used in hardware description languages that effectively guarantees the code model can be synthesized (converted to real logic functions) in a given hardware platform such as an FPGA.

One of the key aspects of true RTL coding in an HDL is the fact that program code processes (or assignments and statements) are concurrent and continuous, unlike RTL coding for a CPU which is a sequential machine and traditionally only executes one instruction at a time (e.g. per instruction cycle).

HDLs provide many sequential language constructs and other features which support modeling and simulation of the designed hardware, however these are not considered part of RTL design as they are simulatable but not easily synthesizable. An example of this would be the write() function used to write the results of the simulation to disk during the execution of a VHDL test bench. Another example would be the VHDL transport statement which infers a fixed propagation delay - something that cannot be directly synthesized by synthesis software.

There are many hardware description languages that can be used to create RTL modules for logic synthesis. Some of the most popular RTL modeling languages include:
* System Verilog
* Verilog
* VHDL

History

The idea behind RTL was first described in:Davidson and Fraser; The Design and Application of a RetargetablePeephole Optimizer; ToPLaS v2(2) 191-202 (April 1980)

References

External links

* [http://gcc.gnu.org/onlinedocs/gccint/RTL.html Register Transfer Language of GNU GCC]