3DNow!

3DNow! is the trade name of a multimedia extension created by AMD for its processors, starting with the K6-2 in 1998. It is an addition of SIMD instructions to the traditional x86 instruction set, designed to improve a CPU's ability to perform the vector processing requirements of many graphic-intensive applications.

History

3DNow! was originally developed as an enhancement to the MMX instruction set. The original idea behind its creation was to extend it from only operating on integer math to also accelerating floating-point calculations.

The "strategic" and "marketing" need to provide for 3D calculations in the floating-point domain was especially needed by AMD. The K6 processor at the time was not well equipped for intensive floating-point mathematics in comparison to the Intel Pentium II.

The 3DNow! instruction set was created during the late 1990s when 3D graphics was exploding in popularity because of 3D gaming, and 3D games heavily use floating-point arithmetic.

Whereas earlier in the 1990s AMD could easily get by with limited floating-point performance, because the vast majority of software was integer-calculation-based, with which the K6 was extremely proficient, 3D gaming and advanced multimedia applications were quickly changing the landscape.

Versions

3DNow!

The first implementation of 3DNow! technology contains 21 new instructions that supported SIMD floating-point operations. The 3DNow! data format is packed, single-precision, floating-point. The 3DNow! instruction set also includes operations for SIMD integer operations, data prefetch, and faster MMX-to-floating-point switching. Later, Intel would add similar (but incompatible) instructions to the Pentium III, known as SSE.

3DNow! floating-point instructions
* PAVGUSB - Packed 8-bit unsigned integer averaging
* PI2FD - Packed 32-bit integer to floating-point conversion
* PF2ID - Packed floating-point to 32-bit integer conversion
* PFCMPGE - Packed floating-point comparison, greater or equal
* PFCMPGT - Packed floating-point comparison, greater
* PFCMPEQ - Packed floating-point comparison, equal
* PFACC - Packed floating-point accumulate
* PFADD - Packed floating-point addition
* PFSUB - Packed floating-point subtraction
* PFSUBR - Packed floating-point reverse subtraction
* PFMIN - Packed floating-point minimum
* PFMAX - Packed floating-point maximum
* PFMUL - Packed floating-point multiplication
* PFRCP - Packed floating-point reciprocal approximation
* PFRSQRT - Packed floating-point reciprocal square root approximation
* PFRCPIT1 - Packed floating-point reciprocal, first iteration step
* PFRSQIT1 - Packed floating-point reciprocal square root, first iteration step
* PFRCPIT2 - Packed floating-point reciprocal/reciprocal square root, second iteration step
* PMULHRW - Packed 16-bit integer multiply with rounding

3DNow! performance-enhancement instructions
* FEMMS - Faster entry/exit of the MMX or floating-point state
* PREFETCH/PREFETCHW - Prefetch at least a 32-byte line into L1 data cache

3DNow! extensions

There is little or no evidence that the second version of 3DNow! was ever officially given its own trade name. This has led to some confusion in documentation that refers to this new instruction set. The most common terms are Extended 3DNow!, Enhanced 3DNow! and 3DNow!+. The phrase "Enhanced 3DNow!" can be found in a few locations on the AMD website but the capitalization of "Enhanced" appears to be either purely grammatical or used for emphasis on processors that may or may not have these extensions (the most notable of which references a benchmark page for the K6-III-P that does not have these extensions).cite web
url=http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/22466.pdf
title=AMD Extensions to the 3DNow! and MMX Instruction Sets Manual
format=PDF
publisher=Advanced Micro Devices, Inc.
date=March 2000
accessdate=2008-06-07] [cite web
url=http://www.amd.com/us-en/Processors/ProductInformation/0,,30_118_1260_1300%5E960,00.html
title=Mobile AMD-K6-III-P Processor-Based Notebook: Ziff-Davis CPUmark 99
quote=Incorrect title on page: Mobile AMD-K6-III+ and Mobile AMD-K6-2+ Processors with Enchanced ["sic"] 3DNow! Technology
accessdate=2008-06-07]

This extension to the 3DNow! instruction set was introduced with the first-generation Athlon processors. The Athlon added 5 new 3DNow! instructions and 19 new MMX instructions. Later, the K6-2+ and K6-III+ (both targeted at the mobile market) included the 5 new 3DNow! instructions, leaving out the 19 new MMX instructions. The new 3DNow! instructions were added to boost DSP. The new MMX instructions were added to boost streaming media.

3DNow! or MMX extensions?

The 19 new MMX instructions are a subset of Intel's SSE1 instruction set. In AMD technical manuals, AMD segregates these instructions apart from the 3DNow! extensions. In AMD customer product literature, however, this segregation is less clear where the benefits of all 24 new instructions are credited to enhanced 3DNow! technology. [cite web
url=http://www.amd.com/us-en/Processors/ProductInformation/0,,30_118_1260_759%5E1151,00.html
title=AMD Athlon Processor Product Brief
publisher=Advanced Micro Devices, Inc.
accessdate=2008-06-08] This has led programmers to come up with their own name for the 19 new MMX instructions. The most common appears to be Integer SSE (ISSE). [cite web
url=http://avisynth.org/mediawiki/ISSE
title=ISSE
publisher=AviSynth
accessdate=2008-06-08] SSEMMX and MMX2 are also found in video filter documentation from the public domain sector. [It should also be noted that ISSE could also refer to Internet SSE, an early name for SSE.]

3DNow! extension DSP instructions
* PF2IW - Packed floating-point to integer word conversion with sign extend
* PI2FW - Packed integer word to floating-point conversion
* PFNACC - Packed floating-point negative accumulate
* PFPNACC - Packed floating-point mixed positive-negative accumulate
* PSWAPD - Packed swap doubleword

MMX extension instructions (Integer SSE)
* MASKMOVQ - Streaming (cache bypass) store using byte mask
* MOVNTQ - Streaming (cache bypass) store
* PAVGB - Packed average of unsigned byte
* PAVGW - Packed average of unsigned word
* PMAXSW - Packed maximum signed word
* PMAXUB - Packed maximum unsigned byte
* PMINSW - Packed minimum signed word
* PMINUB - Packed minimum unsigned byte
* PMULHUW - Packed multiply high unsigned word
* PSADBW - Packed sum of absolute byte differences
* PSHUFW - Packed shuffle word
* PEXTRW - Extract word into integer register
* PINSRW - Insert word from integer register
* PMOVMSKB - Move byte mask to integer register
* PREFETCHNTA - Prefetch using the NTA reference
* PREFETCHT0 - Prefetch using the T0 reference
* PREFETCHT1 - Prefetch using the T1 reference
* PREFETCHT2 - Prefetch using the T2 reference
* SFENCE - Store fence

3DNow! Professional

3DNow! Professional does not appear to be an extension to the 3DNow! instruction set but rather a trade name created to indicate processors that combine 3DNow! technology with a complete SSE instructions set (such as SSE1, SSE2 or SSE3). [cite web
url=http://www.amd.com/us-en/Processors/SellAMDProducts/0,,30_177_4458_4513%5E1413%5E2137,00.html
title=Explaining the new 3DNow! Professional Technology
publisher=Advanced Micro Devices, Inc.
accessdate=2008-06-08] The first processor to match this description would be the Athlon XP. The Athlon XP added the remainder of the SSE1 instruction set missing from earlier Athlon processors (for the total of: 21 original 3DNow! instructions; 5 3DNow! extension DSP instructions; 19 MMX extension instructions; and 52 additional SSE instructions for complete SSE1 compatibility). [cite web
url=http://www.amd.com/us-en/Processors/SellAMDProducts/0,,30_177_4458_3505%5E3785%5E3738,00.html
title=AMD Athlon™ XP Architectural Features
publisher=Advanced Micro Devices, Inc.
accessdate=2008-06-08]

3DNow! and the Geode GX/LX

The Geode GX and Geode LX added 2 new 3DNow! instructions which are currently absent in all the other processors.

3DNow! Professional instructions unique to the Geode GX/LX
* PFRSQRTV - Reciprocal square root approximation for a pair of 32-bit floats
* PFRCPV - Reciprocal approximation for a pair of 32-bit floats

Advantages and disadvantages

One advantage of 3DNow! is that it is possible to add or multiply the two numbers that are stored in the same register. With SSE, each number can only be combined with a number in the same position in another register. This capability, known as "horizontal" in Intel terminology, was the major addition to the SSE3 instruction set.

A disadvantage with 3DNow! compared to SSE is that it only stores two numbers in a register, as opposed to four in SSE. However, 3DNow! instructions can generally be executed with a lower latency and quicker throughput than SSE instructions.

3DNow! also shares the same physical registers as MMX, while SSE has its own independent registers. Because these MMX and 3DNow! registers are also used by the standard x87 FPU, 3DNow! instructions and x87 instructions cannot be executed simultaneously. However, because it is aliased to the x87 FPU, the 3DNow! & MMX register states can be saved and restored by the traditional x87 FNSAVE and FRSTR instructions. Using the pre-existing x87 instructions meant that no operating system modifications had to be made to support 3DNow!.

By contrast, to save and restore the state of SSE registers required the use of the newly added FXSAVE and FXRSTR instructions; the FX* instructions are an upgrade to the older x87 save and restore instructions because these could save not only SSE register states but also those x87 register states (hence which meant that it could save MMX and 3DNow! registers too).

On AMD Athlon XP and K8-based cores (i.e. Athlon 64), assembly programmers have noted that it is possible to actually use both 3DNow! and SSE at the same time. Although both share the same functional unit, this can allow more performance by avoiding some register pressure, but it is difficult to accomplish. [http://groups.google.com/group/comp.sys.ibm.pc.hardware.chips/browse_thread/thread/9da2d940c5b69745]

Processors supporting 3DNow!

* All AMD processors after K6-2 (inclusive)
* National Semiconductor Geode, later AMD Geode.
* VIA C3 (also known as Cyrix III) "Samuel", "Ezra", and "Eden" cores.
* IDT Winchip 2

References

External links

* [http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/22621.pdf AMD 3DNow! Instruction Porting Guide (PDF)]
* [http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/21928.pdf 3DNow!Technology Manual]
* [http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/22466.pdf AMD Extensions to the 3DNow! and MMX Instruction Sets Manual]
* [http://www.amd.com/files/connectivitysolutions/geode/geode_lx/33234E_LX_databook.pdf AMD Geode LX Processors Data Book]
* [http://www.amd.com/us-en/Processors/SellAMDProducts/0,,30_177_4458_4513%5E1413%5E2137,00.html Explaining the new 3DNow! Professional Technology]