Dynamic timing verification
- Dynamic timing verification
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Dynamic timing verification refers to verifying that an ASIC design is fast enough to run without errors at targeted clock rate. This is accomplished by simulating the design files used to synthesize the Integrated Circuit design. This is in contrast to static timing analysis which has a similar goal as dynamic timing verification except does not require simulating the real functionality of the IC.[1]
Hobbies often perform a type of Dynamic timing verification when they over clock the CPU in their computer in order to find the fast clock rate at which they can run the CPU without errors. This is a type of dynamic timing verification that is performed after the silicon is manufactured. In field of ASIC design, this timing verification is preferably performed before manufacturing the IC in order to make sure that IC works under the required conditions before mass production of the IC.[2]
References
- ^ "ASIC world: vol 10", page 13, October 2003
- ^ "ASIC world: vol 10", page 13, October 2003
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