Dual independent bus

Dual independent bus

Dual Independent Bus (DIB) is a processor architecture that includes two buses: one to the main system memory and another to the level 2 cache. The processor can access both simultaneously for improved performance.

In Dual Independent Bus (DIB) architecture systems the single system bus is replaced by a back-side bus for accessing level 2 cache, and a front-side bus for communicating data between the CPU and main memory and input and output devices.


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