Single event upset

A single event upset (SEU) is a change of state caused by a low-energy ions or electro-magnetic or nuclear radiation interferences strike to a sensitive node in a micro-electronic device, such as in a microprocessor, semiconductor memory, or power transistors. The error in device output or operation caused as a result of the strike is called an SEU or a soft error. The SEU itself is not considered permanently damaging to the transistor's or circuits' functionality unlike the case of single event latchup (SEL), single event gate rupture (SEGR), or single event burnout (SEB).

Terrestrial SEU arise due to cosmic particles colliding with atoms in the atmosphere, creating cascades or showers of neutrons and protons, which in turn may interact with electronics. At deep sub-micrometre geometries, this affects semiconductor devices in the atmosphere.

In space, high energy, ionizing particles exist as part of the natural background, referred to as galactic cosmic rays (GCR). Solar activity and trapping of charged particles in the earth's magnetosphere exacerbate the problem. The high energies associated with the space particle environment generally render increased spacecraft shielding useless in terms of eliminating SEU and catastrophic single event phenomena (may cause destructive latch-up, described below). Similar energies are possible on a terrestrial flight over the poles or at high altitude. Trace amounts of radioactive elements in chip packages also lead to SEUs.

The sensitivity of a device to SEU can be empirically estimated by placing a test device in a particle stream at a cyclotron or other particle accelerator facility. This particular test methodology is especially useful for predicting the SER (soft error rate) in known space environments, but can be problematic for estimating terrestrial SER from neutrons. In this case, a large number of parts must be evaluated, possibly at different altitudes, to find the actual rate of upset. When testing microprocessors for SEU, the software used to exercise the device must also be evaluated to determine which sections of the device were activated when SEUs occurred.

By definition, SEUs are non-destructive events. Howevever, under the proper circumstances (of both circuit design, process design, and particle properties) a "parasitic" thyristor inherent to CMOS designs can be activated, effectively causing an apparent short-circuit from power to ground. This condition is referred to as "latchup", and in absence of constructional countermeasures often destroys the device from thermal runaway. Most manufacturers design to prevent latch-up, and test their products to ensure that latch-up does not occur from atmospheric particle strikes. In order to prevent latch-up in space, epitaxial substrates, silicon on insulator (SOI) or silicon on sapphire (SOS) are often used to further reduce or eliminate the susceptibility.

Single event upsets were first described during above ground nuclear testing, from 1954 to 1957, when many anomalies were observed in electronic monitoring equipment. Further problems were observed in space electronics during the 1960s, although it was difficult to separate soft-fails from other forms of interference. In 1978 the first evidence of soft errors from alpha particles in packaging materials was described by Timothy C. May and M.H. Woods. In 1979 James Ziegler of IBM, joined with W. Lanford of Yale, first described the mechanism whereby sea level cosmic ray could cause single event upsets in electronics.

In digital and analog circuits, a single event may cause one or more voltages pulses (i.e. glitches) to propagate through the circuit, in which case it is referred to as a single-event transients. Since the propagating pulse is not technically a change of "state" as in a memory SEU, one should differentiate between SET and SEU. If a SET propagates through digital circuitry and results in an incorrect value being latched in a sequential logic unit, it is then considered an SEU.

See also Radiation hardening.

References

General SEU

* T.C. May and M.H. Woods, IEEE Trans Electron Devices ED-26, 2 (1979)
* [http://www.seutest.com www.seutest.com] - Soft-error testing resources to support the JEDEC JESD89A test protocol.
* J. F. Ziegler and W. A. Lanford, "Effect of Cosmic Rays on Computer Memories", "Science", 206, 776 (1979)
* [http://www.research.ibm.com/journal/rd40-1.html Ziegler, et al. IBM Journal of Research and Development. Vol. 40, 1 (1996)] .
* [http://radhome.gsfc.nasa.gov/radhome/see.htm NASA Introduction to SEU] from Goddard Space Flight Center Radiation Effects Facility
* [http://adsabs.harvard.edu/cgi-bin/nph-abs_connect NASA/Smithsonian abstract search] .
* "Estimating Rates of Single-Event Upsets", J. Zoutendyk, "NASA Tech Brief", Vol. 12, No. 10, item #152, Nov. 1988.
* [http://www.boeing.com/assocproducts/radiationlab/publications/ Boeing Radiation Effects Laboratory, focussed on Avionics]
* [http://www.usenix.org/events/usenix07/tech/li.html A Memory Soft Error Measurement on Production Systems, 2007 USENIX Annual Technical Conference, pp. 275-280]

EU in programmable logic devices

* [http://direct.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=-19240&iLanguageID=1&multPartNum=1&sTechX_ID=al_soft_vs_hard "Single-Event Upsets: Should I Worry?"] Xilinx Corp.
* [http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sTechX_ID=al_v4_soft_error "Virtex-4: Soft Errors Reduced by Nearly Half!"] A. Lesea, Xilinx TecXclusive, 6 May 2005.
* [http://www.actel.com/documents/RadResultsIROCreport.pdf "Radiation Results of the SER Test of Actel, Xilinx and Altera FPGA instances"] , Engineering Test Report, iROC, 25 October 2004.
* [http://www.altera.com/products/devices/stratix/features/stx-seu.html Single Event Upsets] Altera Corp.
* [http://www.rcnp.osaka-u.ac.jp/~annurep/2001/genkou/sec3/kobayashi.pdf Evaluation of LSI Soft Errors Induced by Terrestrial Cosmic rays and Alpha Particles] - H. Kobayashi, K. Shiraishi, H. Tsuchiya, H. Usuki (all of Sony), and Y. Nagai, K. Takahisa (Osaka University), 2001.

SEU in microprocessors

* Elder, J.H.; Osborn, J.; Kolasinski, W. A.; "A method for characterizing a microprocessor's vulnerability to SEU", "IEEE Transactions on Nuclear Science", Dec 1988 v 35 n 6.
* [http://crc.stanford.edu/crc_papers/CRC-TR-01-4.pdf SEU Characterization of Digital Circuits Using Weighted Test Programs]
* [http://www-hpc.jpl.nasa.gov/PEP/pls/papers/Fault_analysis.pdf Analysis of Application Behavior During Fault Injection]
* [http://flightlinux.gsfc.nasa.gov/docs/Target_Arch_Report.html Flight Linux Project]

EU related masters theses and doctoral dissertations

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