Asic verification

Asic verification

ASIC verification is today’s most challenging problem for ASIC designers. As chip sizes have skyrocketed and use of IP has increased, the need to fully verify the design functionality has become critical. However, verification is a function of both design size and vector size.As the design size grows, the required vector size needed to unctionally verify it also grows. A general rule of thumb is for every 10x increase in design size, a 10x increase in vectors is needed to adequately check the unctionality. This means that for every 10x design size increase, the verification problem grows 100x. This explosion in verification effort has forced designers to increasingly look for faster alternatives to their previous methodologies.

Verilog is Hardware design Language , which is also used for functional verification.

A Hardware Verification Language, or HVL, is a programming language used to verify the designs of electronic circuits written in a hardware description language. HVLs typically include features of a high-level programming language like C++ or Java as well as features for easy bit-level manipulation similar to those found in HDLs.

OpenVera, Specman e, and SystemC are the most commonly used HVLs, while SystemVerilog attempts to combine HDL and HVL constructs into a single standard.

References


*


Wikimedia Foundation. 2010.

Игры ⚽ Поможем написать реферат

Look at other dictionaries:

  • Dynamic timing verification — refers to verifying that an ASIC design is fast enough to run without errors at targeted clock rate. This is accomplished by simulating the design files used to synthesize the Integrated Circuit design. This is in contrast to static timing… …   Wikipedia

  • Structured ASIC platform — Structured ASIC is an intermediate technology between ASIC and FPGA, offering high performance, a characteristic of ASIC, and low NRE cost, a characteristic of FPGA.Using Structured ASIC allows products to be introduced quickly to market, to have …   Wikipedia

  • Clock Domain Crossing Verification — Clock domain crossing (CDC) verification is a vital part of today ASIC designs, and hence an integral part of electronic design automation process. Commercial applications for CDC checking Major products in the CDC Verification area of EDA are:*… …   Wikipedia

  • Application-specific integrated circuit — An application specific integrated circuit (ASIC) is an integrated circuit (IC) customized for a particular use, rather than intended for general purpose use. For example, a chip designed solely to run a cell phone is an ASIC.In contrast, the… …   Wikipedia

  • Verilog — In the semiconductor and electronic design industry, Verilog is a hardware description language (HDL) used to model electronic systems. Verilog HDL , not to be confused with VHDL, is most commonly used in the design, verification, and… …   Wikipedia

  • XAP processor — The XAP processor is a RISC processor architecture developed by Cambridge Consultants Ltd since 1994. XAP processors are a family of 16 bit and 32 bit cores, all of which are intended for use in an application specific integrated circuit or ASIC… …   Wikipedia

  • Aldec — Infobox Company company name = ALDEC, Inc. company company type = Private foundation = 1984 location = Henderson, Nevada, United States flagicon|USA industry = EDA products = Active HDL, Riviera, SFM, HES homepage = [http://www.aldec.com… …   Wikipedia

  • Hardware description language — In electronics, a hardware description language or HDL is any language from a class of computer languages and/or programming languages for formal description of electronic circuits. It can describe the circuit s operation, its design and… …   Wikipedia

  • Firepower International — was advertised as a Hong Kong based company owned and operated by Global Fuel Technologies Ltd, specializing in technology purporting to reduce the fuel consumption and environmental impact of petrol operated vehicles.[1] There were other offices …   Wikipedia

  • Standard cell — For the battery used as a voltage reference, see Weston cell. In semiconductor design, standard cell methodology is a method of designing Application Specific Integrated Circuits (ASICs) with mostly digital logic features. Standard cell… …   Wikipedia

Share the article and excerpts

Direct link
Do a right-click on the link above
and select “Copy Link”