Aldec

Aldec

Infobox_Company
company_name = ALDEC, Inc.
company_
company_type = Private
foundation = 1984
location = Henderson, Nevada,
United States flagicon|USA
industry = EDA
products = Active-HDL, Riviera, SFM, HES
homepage = [http://www.aldec.com aldec.com]

Aldec, Inc. is a privately owned electronic design automation company.

Overview

Aldec provides software and hardware used in creation and verification of digital designs targeting FPGA and ASIC technologies. Headquartered in the USA (Henderson, NV), Aldec has offices in Canada, Japan, Poland and Ukraine.

Products

Software

* Active-HDL - FPGA development environment built around common kernel HDL simulator. Supports text-based and graphical design entry and debugging tools, allows mixed-language simulation (VHDL/Verilog/EDIF/SystemC/SystemVerilog) and provides unified interface to various synthesis and implementation tools. Also supports assertion based verification with Open Vera, PSL, or Systemverilog Assertion statements. Only available on MS Windows platform.

* Riviera - high-end HDL simulator targeting ASIC and large FPGA designs. Riviera includes all of Active-HDL's features and adds advanced verification methodologies such as linting, functional coverage, hardware acceleration, prototyping. Available in 32-bit and 64-bit on MS Windows, Linux, and Solaris.

* Server Farm Manager (SFM) - web-based, regression testing automation solution that automates the scheduling, execution, result analysis, and reporting of tens-to-thousands of parallel simulations from one control point. Platform independent.

* IP Products - a set of general-purpose Intellectual Property blocks created by Aldec and its partners, validated in Active-HDL and Riviera environments.

Hardware

* HES - solution allowing acceleration of HDL simulation (10x to 50x verification time reduction), emulation of the entire design (e.g. prototyping of an ASIC using FPGAs) and hardware/software co-simulation (useful in Embedded System development).

Education

Aldec provides fully functional, heavily discounted versions of its software for educational institutions worldwide (Kumaon Engineering College, [http://www.ntu.edu/PD/pdcourse.asp?CID=OL03012299 National Technology University] ).

Aldec also offers a special Student-Edition of Active-HDL, downloadable from Aldec's website. The Student-Edition has limited design capacity and some reduction of program functionality, but supports both design languages (Verilog/VHDL.)

The company also supports local education - in 1999 it contributed to the establishment of the "Aldec Digital Design Laboratory" at the UNLV. [ECE-UNLV staff, [http://www.ee.egr.unlv.edu/05EngNews.pdf "ALDEC, (...) plays a significant role in ECE programs"] ,Page 3, ECE-UNLV News, Vol 5, 2005]

Aldec software is packaged with several electronic design related books (e.g. [http://vig.prenhall.com/catalog/academic/product/0,1144,0131733494,00.html "Digital Design: Principles and Practices"] , [http://vig.prenhall.com/catalog/academic/product/0,1144,0132188244,00.html "CONTEMPORARY LOGIC DESIGN"] ).

History

* Aldec was founded in 1984 by Dr. Stanley M. Hyduke.

* In 1985 the company released its first product: MS DOS-based gate-level simulator SUSIE. For the next couple of years several versions of the product were used as companion simulators for popular schematic entry tools such as OrCAD.

* Sensing growing popularity of Microsoft Windows, ALDEC ported its simulator to this platform and added schematic entry and design management tool. The new software suite was released in 1992 as Active-CAD (some low-end versions of the suite were for some time sold under Susie-CAD brand). One of the distinguishing features of Active-CAD was the ability of instantaneous transfer of schematic changes to the simulator, allowing quick verification of the behavior of the modified circuit.
* In 1996 Aldec signed agreement with Xilinx that allowed distribution of Xilinx-only version of Active-CAD under the Foundation name.

* While VHDL and Verilog were supported by Active-CAD in the form of schematic macros, the release of Active-VHDL in 1997 marked the shift from netlist-based design to HDL-based design. After adding Verilog support, Active-VHDL was renamed to Active-HDL and is still available (as of 2007).

* In 2000 ALDEC released high-performance HDL simulator working not only on Windows, but also on Solaris and Linux platforms. [Richard Goering, [http://www.eetimes.com/story/OEG20001113S0089 "Aldec rolls out Linux-based mixed-language simulator"] , EETimes.com, November 132000]

* In 2001 ALDEC added hardware to its product line: HES Platform that allows hardware acceleration of HDL simulation and incremental prototyping of hardware.

* Year 2003 marks the release of Riviera supporting assertion based verification (OpenVera, PSL and SystemVerilog can be used to write properties, assertions and coverage.)

* Support for SystemC and non-assertion part of SystemVerilog was added in 2004. Interfaces to MATLAB and Simulink appeared in Aldec tools for the first time in 2005.

* In 2006 Riviera was the first simulator supporting Open IP Encryption Initiative by Synplicity. [Christine Evans-Pughe, [http://www.electronicsweekly.com/Articles/2006/10/13/39925/protecting+your+ip+just+got+simpler.htm "Protecting your IP just got simpler"] , Paragraph 11, Electronics Weekly, October 132006]

* Stimulated by requests from Verilog users, ALDEC released in 2007 an advanced, user-configurable lint tool implementing rules created by [http://www.starc.jp/index-e.html STARC] - Japanese consortium of major silicon vendors.

Trivia

* Student Edition of Active-HDL was the first HDL simulator to be sold at Walmart. [EDN Online Staff, [http://www.edn.com/article/CA6308640.html "EDA Software Sold in Walmart."] , EDN, February 202006]
* The name of the first Aldec product - SUSIE - is an acronym for "Standard Universal Simulator for Improved Engineering".

See also

* VHDL
* Verilog
* Warp (Cypress)

References

External links

* [http://www.aldec.com Official site]


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