Low Pin Count

The Low Pin Count bus, or LPC bus, is used on IBM-compatible personal computers to connect low-bandwidth devices to the CPU, such as the boot ROM and the "legacy" I/O devices (behind a super I/O chip). The "legacy" I/O devices usually include serial and parallel ports, keyboard, mouse, floppy disk controller and - more recently - the Trusted Platform Module. The physical wires of the LPC bus usually connect to the southbridge chip on a PC motherboard.

The LPC bus was introduced by Intel in 1998 as a substitute for the Industry Standard Architecture (ISA) bus. It resembles ISA to software, although physically it is quite different.

The LPC specification defines seven mandatory signals required for bidirectional data transfer. Four of these signals carry the multiplexed address and data. The other three are control signals (frame, reset and clock).

The six optional signals defined in the specification can be used for interrupt support, direct memory access, waking the system from a low power ("sleeping") state and notifying the LPC peripherals that power will soon be removed.

LPC data transfer rates depend on the type of bus access (I/O, Memory, DMA, Firmware.) In all cases, LPC bus accesses are faster than their ISA equivalents. At 33.3 MHz, the typical I/O transfer rate is about 2.56 Mbyte/s.

LPC's main advantage is that it requires only seven signals, and is therefore easy to route on modern motherboards, which are often quite crowded. An integrated circuit using LPC will need 30 to 72 fewer pins than its ISA equivalent. The clock rate was chosen to match that of PCI in order to further ease integration. Also, LPC is intended to be a motherboard-only bus. No connector is defined, and no LPC peripheral daughterboards are available.

The original Xbox game console has an LPC debug port that is used by modders to run un-signed code on the system.

ee also

*List of device bandwidths

External links

* [http://www.intel.com/design/chipsets/industry/lpc.htm LPC Interface Specification at Intel]
* [http://www.smsc.com/main/tools/papers/serirq60.doc Serialized IRQ Support For PCI Systems] (Microsoft Word format) - used by the LPC bus
* [http://www.opencores.org/projects.cgi/web/wb_lpc/overview Open-Source LPC Host and Peripheral Cores]