Infobox Computer Hardware Bus
name = Q-Bus
fullname = Q-Bus

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invent-name = Digital Equipment Corporation
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The Q-bus (also known as the LSI-11 Bus) was one of several bus technologies used with PDP and MicroVAX computer systems manufactured by the Digital Equipment Corporation of Maynard, Massachusetts.

The Q-bus was a less expensive version of Unibus using multiplexing so that address and data signals shared the same wires. This allowed both a physically smaller and less-expensive implementation of essentially the same functionality.

Over time, the physical address range of the Q-bus was expanded from 16 to 18 and then 22 bits. Block transfer modes were also added to the Q-bus.

Main features of the Q-bus

Like the Unibus before it, the Q-bus used:
* "Memory-mapped I/O"
* "Byte addressing"
* A strict "master-slave" relationship between devices on the bus
* "Asynchronous signaling"

"Memory-mapped I/O" means that data cycles between any two devices, whether CPU, memory, or I/O devices, used the same protocols. On the Unibus, a range of physical addresses were dedicated for I/O devices. The Q-bus simplified this design by providing a specific signal (originally called "BBS7", "Bus Bank Select 7" but later generalized to be called "BBSIO", "Bus Bank Select I/O") that selected the range of addresses used by the I/O devices.

"Byte addressing" means that the physical address passed on the Unibus was interpreted as the address of a byte-sized quantity of data. Because the bus actually contained a data path that was two bytes wide, address bit [0] was subject to special interpretation and data on the bus had to travel in the correct byte lanes.

A strict "Master-Slave" relationship means that at any point in time, only one device could be the "Master" of the Q-bus. This "master device" could initiate data transactions which could then be responded to by a maximum of one selected "slave device". (This had no effect on whether a given bus cycle was reading or writing data; the bus master could command either type of transaction.) At the end of the bus cycle, a "bus arbitration" protocol would then select the next device to be given mastership of the bus.

"Asynchronous signaling" means that the bus had no fixed cycle time; the duration of any particular data transfer cycle on the bus was determined solely by the master and slave devices participating in the current data cycle. These devices used "handshake" signals to control the timing of the data cycle. Timeout logic within the master device limited the maximum allowed length of any given bus cycle.

Depending on its generation, the Q-bus contained 16, 18, or 22 "BDAL" ("Bus Data/Address Line") lines. 16, 18, or 22 BDAL lines were used for the physical address portion of each bus cycle. Eight or 16 DBAL lines were then re-used for the data portion(s) of each bus cycle. Newer generations of the bus allowed "block mode" transfer where a single bus address could be followed by more than one data cycle (with the transfers taking place at consecutive bus addresses). Because the address portion of each bus cycle can not transfer data, the use of block mode meant fewer address cycles and more time for data cycles, allowing increased bus data transfer bandwidth.

Bus mastery was awarded based on an I/O card's geographical proximity to the bus arbitrator (at the logical front of the bus); closer cards were granted priority over further cards.

Interrupts could be delivered to the "Interrupt Fielding Processor" at any of four priority levels. Within a given level, the cards closer to the IFP (at the front of the bus) took priority over cards further back on the bus. Interrupts were vectored: a card requesting an interrupt had its interrupt vector read by the IFP. In this way, the interrupts from all I/O cards in the system could be distinguished with no ambiguity.

Logic minimization

As with the Unibus, the signaling was carefully optimized so that the minimum amount of logic was required across the entire bus system. Asynchronous signaling was used but all responsibility for de-skewing of addresses and data was the responsibility of the current bus master, minimizing the complexity of the bus slave devices. The responsibility for timing-out failed bus cycles also was placed in the master devices. Similarly, the complexities of handling interrupt transactions were concentrated into the single "Interrupt-Fielding Processor" (the PDP-11 or VAX-11 computer) in the system.


The design of the Q-bus was very closely related to the design of the Unibus both in spirit and in detailed implementation. Adapters were available from Digital and from third parties that allowed Q-bus devices to be connected to Unibus-based computers and vice-versa. A number of I/O devices were available in either Unibus or Q-bus flavors; some of these devices had minor differences while many others were essentially identical.

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